SDH TRANSMISSION SYSTEM SDH BASICS

What is SDH? Characteristics of SDH ITU-Ts Recommendations Bit Rates Path and Section Review Questions
1

What is SDH?
A New Digital Hierarchy
155.52 Mb/s, 622.08 Mb/s, 2488.32 Mb/s, 9953.28 Mb/s, 39813.120Mb/s
Existing PDH and future ATM signals are carried over the SDH system.

Very basic functions are same as PDH.

Multiplex low bit rate digital signals to higher bit rate and transmit large information efficiently.

What are the differences ?

Synchronous Network
Basically, all network elements work on a single clock source.

Abundant Overhead Bits

To carry large information for Network Management.

Unified Interface and Multiplexing Specifications

Common to all countries. Standardized optical interfaces.

What are the benefits? (1) - Synchronous Network Simple multiplexing process Easy access to tributary signals in a multiplexed high bit rate signal.

ADD/DROP RING CROSS CONNECT

distribution survivability capacity management band width management protection route diversity

Simple Access to Tributaries

140M 34 M 8M 8M DD F 34M 140M

A D D /D R O P M U X

PDH

2M S T M -1 M IN I X -C O N N ST M -1

SDH
2M

What are the benefits? (2) - Overhead Bits

Realization of highly advanced Network Management System for:
Fault management Configuration management Performance management Security management Accounting management

What are benefits SDH? (3) - Unified Interface

Multi-vendor Environment
International Connection

What are SDH? - in conclusion

SDH is the infrastructure for the telecommunication network of the 21st century, providing board band and intelligent services.

ITU-Ts Recommendations on SDH

G.707 Network Node Interface for the SDH G.773 Protocol Suits for Q-interface G.774 SDH Management Information Model for the Network Element View G.781 Synchronization layer functions G.782 Types and General Characteristics of SDH Multiplexing Equipment G.783 Characteristics of SDH Multiplexing Equipment Functional Blocks G.784 SDH Management G.803 Architecture of Transport Networks Based on the SDH G.813 Timing characteristics of SDH equipment slave clocks(SEC) G.842 Interworking of SDH network protection architectures G.957 Optical Interfaces for Equipments and Systems Relating to SDH G.958 Digital Line Systems Based on SDH for Use on Optical Fiber Cables
8

SDH Bit Rates

CEPT
2.048 Mb/s 8.448 Mb/s 34.368 Mb/s 139.264 Mb/s STM-0 STM-1 STM-4 STM-16 STM-64

North America
1.544 Mb/s 6.312 Mb/s 44.376 Mb/s

Japan
1.544 6.312 32.064 97.728 Mb/s Mb/s Mb/s Mb/s PDH G.702

51.840 Mb/s 155.520 Mb/s 622.080 Mb/s 2,488.320 Mb/s 9,953.280 Mb/s STM: Synchronous Transport Module SDH G.707

STM-256 39,813.120 Mb/s

Path and Section

Path Multiplex Section Regenerator Section Regenerator Section Regenerator Section

MUX

LT REG REG

LT

MUX

VC Processing

STM-N Processing

10

Review Questions
Fill up the following sentences with correct words: A) When the SDH and PDH are compared, the ( 1 ) is an asynchronous system and the ( 2 ) is a synchronous system. The ( 3 ) conforms to the worldwide unique standard. On the other hand, there are three different ( 4 ) standards, for Europe and others, North America, and Japan. B) The peculiarities of the SDH are that the entire network basically operates with one ( 1 ), it conforms to the ( 2 ) recommendation, and advanced ( 3 ) is easily enabled by using abundant ( 4 ). C) The bit rate of STM-1 is ( 1 ) Mb/s, bit rate of STM-4 is ( 2 ) Mb/s, and bit rate of STM-16 is ( 3 ) Mb/s. They are ( 4 ) multiple of STM- ( 5 ). D) The regenerator section is a section between ( 1 ) ( 2 ) or a section between a ( 3 ) and its neighbor ( 4 ). E) The multiplex section is a section between nodes where ( 1 ) is generated and ( 2 ). F) The path is a connection between assembling and disassembling points of ( 1 ).

11

12

SDH TRANSMISSION SYSTEM MULTIPLEXING STRUCTURE, FRAME STRUCTURE AND POINTER

Multiplexing Structure Frame Structure Pointer Review Questions
13

SDH Multiplexing Structure (1)

X1 x1

STM-256

AUG-256
x4 X1 x1

AU-4-256c

VC-4-256c

C-4-256c

STM-64

AUG-64
x4 x1

AU-4-64c

VC-4-64c

C-4-64c

STM-16

X1

AUG-16
x4 x1

AU-4-16c

VC-4-16c

C-4-16c

STM-4

X1

AUG-4
x4 x1

AU-4-4c

VC-4-4c

C-4-4c

STM-1

X1

AUG-1
x3

AU-4

VC-4
x3

C-4 TUG-3
x1 TU-3

139264 kb/s

VC-3 C-3 44736 kb/s 34368 kb/s 6312 kb/s

STM-0

X1

AU-3

VC-3

x7

x7 x1

TUG-2

TU-2
x3

VC-2 VC-12

C-2

Poi nt er pr ocessi ng Multiplexing Aligning Mapping

TU-12
x4

C-12 2048 kb/s

TU-11

VC-11

C-11 1544 kb/s

14

SDH Multiplexing Structure (2)

X1 x1

STM-256

AUG-256
x4 X1 x1

AU-4-256c

VC-4-256c

C-4-256c

STM-64

AUG-64
x4 x1

AU-4-64c

VC-4-64c

C-4-64c

STM-16

X1

AUG-16
x4 x1

AU-4-16c

VC-4-16c

C-4-16c

STM-4

X1

AUG-4
x4 x1

AU-4-4c

VC-4-4c

C-4-4c

STM-1

X1

AUG-1
x3

AU-4

VC-4
x3

C-4 TUG-3
x1 TU-3

139264 kb/s

VC-3 C-3 44736 kb/s 34368 kb/s 6312 kb/s

STM-0

X1

AU-3

VC-3

x7

x7 x1

TUG-2

TU-2
x3

VC-2 VC-12

C-2

Poi nt er pr ocessi ng Multiplexing Aligning Mapping

TU-12
x4

C-12 2048 kb/s

TU-11

VC-11

C-11 1544 kb/s

15

Multiplexing Process of SDH

Example: 2 Mb/s to STM-4
2.048Mb/s S 2.048Mb/s LO POH TU-1 PTR TU-1 PTR 3 TU-1 PTR 2 TU-1 PTR 1 pointer offset value C-12

PDH C-12 VC-12 TU-12

VC-12 VC-12
1 2

VC-12
7

1 3

VC-12 TUG-2

1 1

TUG-2 TUG-3 VC-4 AU-4 AUG-1

TUG-2
HO POH AU-4 PTR pointer offset value

TUG-3

TUG-3

TUG-3

VC-4 VC-4
4

AU-4 PTR

AUG-1
SOH

AUG-1

AUG-1

AUG-1

AUG-4 STM-4
16

AUG-4

STM-1 Frame Structure

1 2 3 4 5 6 7 8

8 bits = 1 byte

125 s ( 1) ( 2) ( 9)

270 bytes
9 ( 1) ( 2) 3 1 261

R-SOH AU PTR Payload Capacity

9 rows

M-SOH

( 9)

270 columns

125 s

R-SOH: Regenerator Section Overhead M-SOH: Multiplex Section Overhead

17

Byte Interleaved Multiplex and Frame Structure STM-N

STM-1 (AU-4) STM-N

STM-1 STM-1 STM-1 STM-1

AAA BBB CCC NNN

AU-4 AU-4 AU-4

CBA N STM-N

CBA

AU-4

byte interleaved multiplexing

261 x N

9 x N

R SOH
9 rows

ABC

NABC

AU PTRs

M SOH

N 125 s

18

Pointer Function
R SOH VC-4(1) VC-4(2) VC-4(3) AU PTR P O H TU12 PTR

POH
VC-12

M SOH

TU-3 PTR area

POH
VC-12

POH
VC-12

(
V C 4

STM-4

)
2 M signal Example: 2 Mb/s to STM-4 via AU-4 VC-4 (4) VC-12 (63)
63 2 1
19

AU-4 Pointer and Pointer Offset Number

H1 * * H2 * * H3H3H3

0 0 0 1 1 1 87 # #

86 # #

VC-4

435 # # 522 # # 696 # #

521 # #

782 # #

H1

H2

NNNNSS I D I D I D I D I D 10 bits

same number for 3 consecutive bytes

Pointer Configuration

20

TU-12 Pointer and Pointer Offset Numbering

V1 105 36 bytes 35 bytes 139 V2 0 125 s V1 V5

125 s

V2

J2

20
34 V3 35

V5 Z6 V3

V1

V2

N N N N S S I D I D I D I D I D 10 bits
69 V4 70 K4

Pointer Structure
V4

*In this case, pointer offset value is set 20(0000010100)

104

500 s

VC-12 TU-12
500 s

21

Pointer Renewal
A

STM-1

STM-N
AB

STM-1

input signal
A

multiplexed signal
delay

(
B

STM-1

STM-1
delay

)
frame aligned signal

22

AU-4 Justification (1)

1

Negative justification opportunity (3 bytes)

4
0 0 0

Positive justification opportunity (3 byte)

9
Negative justification control invert five D-bits accept majority vote Positive justification control invert five I-bits accept majority vote

H1

H2

I : Increment bit
D : Decrement bit N : New data flag bit

N N N N S S I D I D I D I D I D

pointer value

23

AU-4 Justification (2) - Positive Justification start of VC-4

H1 Y Y H2 1 1 H3 H3 H3 n-1 n n n n+1 n+1 Frame 1 125 s

pointer value (n)

H1 Y Y H2 1 1 H3 H3 H3 n-1 n n n n+1 n+1 Frame 2 250 s

pointer value (I bits inverted)

H1 Y Y H2 1 1 H3 H3 H3

positive justification
n-1 n n n n+1 n+1

start of VC-4 (new)

Frame 3

375 s

pointer value (n+1)

H1 Y Y H2 1 1 H3 H3 H3 n-1 n n n n+1 n+1 Frame 4 500 s

24

AU-4 Justification (3) - Negative Justification start of VC-4

H1 Y Y H2 1 1 H3 H3 H3 n-2 n-1 n-1 n-1 n n n n+1 n+1 Frame 1 125 s

pointer value (n)

H1 Y Y H2 1 1 H3 H3 H3 n-2 n-1 n-1 n-1 n n n n+1 n+1 Frame 2 250 s

H1 Y

Y H2 1

pointer value (D bits inverted) start of VC-4 (new) negative justification

n-2 n-1 n-1 n-1 n n n n+1 n+1 Frame 3 375 s

pointer value (n-1)

H1 Y Y H2 1 1 H3 H3 H3 n-2 n-1 n-1 n-1 n n n n+1 n+1 Frame 4 500 s

25

Review Questions
Fill up the spaces enclosed in parentheses in the following sentences with correct words: 1. The cycle of the frame structure of STM-1 is ( a ) and composed of ( b ) bytes. ( c ) vertical matrixes and ( d ) horizontal matrixes represent the frame structure. 2. An STM-4 signal has four times the rate of an STM-1 signal. The STM-4 signal has rate of ( a )Mbit/s (=( b )x( c )Mbit/s). There are 36 columns for section overhead plus ( d ) pointer. There are ( e ) columns or byte for an STM-4 signal. 3. Multiplexing process route via AU-( a ) is ( b ) standard and used in most countries. One AUG is equivalent one ( c ). A three of ( d ) signals is formed an AUG. 4. VC-3 or VC-4 POH starts immediately after ( a ) (if the pointer offset value is 0); but for VC12 POH, V5 is placed right after the ( b ) byte not after the ( c ). 5.. The five I bits in the (H1, H2) pointer word are inverted if the system request a ( a ) frequency justification while the five D bits used for ( b ) frequency justification. In either case, the majority vote rule is applicable to both the I and the D bits. Under a normal operation condition, the pointer value can be increased or decreased by ( c ). If the pointer value is 728, and a positive frequency justification is requested, the new pointer value will become ( d ) for the next three frames. If the pointer value is 0, and a negative frequency justification is requested, the new pointer value will become ( e ) for the next three frames. 6. The NDF of SDH pointer has a code of ( a ) for a normal operation; on the other hand, for restarting (rebooting ) a new pointer while ignoring the existing one, NDF should be set to ( b ).

26

27

28

SDH TRANSMISSION SYSTEM

OVERHEAD AND MAPPING

Overhead Mapping Review Questions

29

STM-1 Frame Structure and SOH

9 bytes 261 b ytes RSO H
9 row s

A U P TR STM-1 PAYLOAD MSOH

S ec tion O verhead

A1 A1 B1 D1 B2 B2 D4 D7 D10 S1 Z1

A1

A2 A2 A2 E1 D2 AU Pointer(s) B2 K1 D5 D8 D11 Z1 Z2 Z2 M1

J0 F1 D3 K2 D6 D9 D12 E2

RSOH

MSOH

: bytes reserved for national use

30

Function of SOH (1)

Framing Regenerator section trace Data communication channel Order wire User channel Error monitoring APS signaling (A1, A2) (J0) (D1-3) (D4-12) (E1) (E2) (F1) (B1) (B2) (K1,2) (K2) (S1) (M1) regenerator section connection check regenerator section DCC, 192 kb/s multiplex section DCC, 576 kb/s accessible at regenerators accessible at multiplexers 64 kb/s clear channel regenerator section BIP-8 multiplexer section BIP-24N automatic protection switching also used as MS-AIS and MS-RDI indication of quality level REI (count of BIP-24N) RDI ; Remote Defect Indication (formerly FERF, Far End Receive Failure) ; Remote Error Indication (formerly FEBE, Far End Block Error) ; Multiplex Section ; Data Communication Channel

Synchronization status Section status reporting

A1 B1 D1 A1 A1 A2 A2 A2 J0 E1 F1 D2 D3 AU Pointer(s) B2 K1 K2 D5 D6 D8 D9 D11 D12 Z1 Z2 Z2 M1 E2

RSOH

B2 B2 D4 D7 D10 S1 Z1

REI

MSOH

: bytes reserved for national use

MS DCC

31

Function of SOH (2)

Framing Regenerator section trace Data communication channel Order wire User channel Error monitoring APS signaling (A1, A2) (J0) (D1-3) (D4-12) (E1) (E2) (F1) (B1) (B2) (K1,2) (K2) (S1) (M1) regenerator section connection check regenerator section DCC, 192 kb/s multiplex section DCC, 576 kb/s accessible at regenerators accessible at multiplexers 64 kb/s clear channel regenerator section BIP-8 multiplexer section BIP-24N automatic protection switching also used as MS-RDI indication of quality level REI (count of BIP-24N) RDI ; Remote Defect Indication (formerly FERF, Far End Receive Failure) ; Remote Error Indication (formerly FEBE, Far End Block Error) ; Multiplex Section ; Data Communication Channel

Synchronization status Section status reporting

A1 B1 D1 A1 A2 A2 A2 J0 E1 F1 D2 D3 AU Pointer(s) B2 K1 K2 D5 D6 D8 D9 D11 D12 Z1 Z2 Z2 M1 E2 A1

RSOH

B2 B2 D4 D7 D10 S1 Z1

REI
MSOH

; bytes reserved for national use

MS DCC

32

Section and Path Trace Method

Node A LPT HPT MST RST RST Node B MST HPT LPT

RST J0: Section trace VC-4 POH (J1: Path trace) VC-3 POH(J1: Path trace) VC-12(J2: Path trace) RST: Regenerator Section Termination MST: Multiplex Section Termination HPT: High Order Path Termination LPT: Lower Order Path Termination

Path Trace

Node -A : Used

Node -B Path Trace : Used Transmit path trace : ABCDEFG Path Trace expected value : 123-565656 Received value : 123-565656
33

Transmit path trace : 123-565656 Path Trace expected value : ABCDEGF Received value : ABCDEFG

Section Trace(J0)
Node A R S T a c b d Node B R S T R S T Node C R S T

R S T

a c

b d

R S T Terminated Section of Section Trace

Terminated Section of Section Trace RST: Regenerator Section Termination

34

Principle of BIP 8
1121 * * * K1 * * * 81 12 22 * * * K2 * * * 82

#n Block

1i 2i * * * Ki * * * 8i

1n 2n * * * Kn * * * 8n 1 2 * * * ** K * * * * 8 # n+1 Block B1 byte

Ki =
1

even - - - - - K=0 odd - - - - - K=1

35

BIP Computing Area

RSOH AU PTR counted after scrambling

RSOH

#n

A U PTR counted before scram bling

MSOH

M SOH

B1 B1 renewed at every regenerator

# n+1

B2 B2 B2 B2 renewed only at m ultiplexer

BIP 8 for Regenerator Section

BIP N x 24 for Multiplex Section

36

Higher-Order POH Functions (VC-3, VC-4)

Path error monitor Path status report
VC-3 / VC-4

(B3) (G1)

J1 B3 C2 G1 F2 H4 F3 K3 N1
V C -3 / VC-4 pa yload

Path trace Signal label

(J1) (C2)

Path user channels APS signaling Position indicator Network operator byte

(F2, F3) (K3) (H4) (N1)

BIP-8 REI (Remote Error Indication) count of error (BIP-8 results) RDI (Remote Defect Indication) receiving path AIS, signal failure path trace mismatch verification of VC connection user programmable, 15 characters indication of VC composition unequipped, equipped-non-specific, TUG structure, locked TU, ATM, async. 34M or 45M, async. 140M, MAN (DQDB), FDDI 64 kb/s clear channels automatic protection switching at the higher order path level multiframe position for the VC-1, VC-2 for tandem connection maintenance

REI; formerly FEBE (Far End Block Error), RDI; formerly FERF (Far End Receive Failure)

37

TU-12 multiframe indication byte

VC-3/VC-4 POH Portion

(V4)
VC-3/VC-4 Payload
9 rows

H4(00)

PTR(V1)
VC-3/VC-4 Payload

H4(01)

PTR(V2)
VC-3/VC-4 Payload

1 X X X X

2 X X X X

3 1 1 1 1

H4 bits 4 5 6 1 X X 1 X X 1 X X 1 X X

7 0 1 1 1

8 1 0 0 1

Frame No 0 1 2 3

Time 0 500s TU-n multiframe

H4(10)

X: Bit reserved for future international standardization. Its content shall be set to 1" in the interim.
PTR(V3)
VC-3/VC-4 Payload

H4(11)

(V4)
VC-3/VC-4 Payload

H4(00)

In H4(X Y), X Y represent bits 7 and 8 of H4

38

Path Trace (J1)

Node A a c b d L P T Node B Cross connection Node C

L P T

Terminated Section of J1 (J2) Path Trace LPT: Lower Order Path Termination [It will change to HPT(High Order Path Termination) when VC-4 J1 is used]

39

Tandem Connection
A Network B Network (Operator Administrative area) C Network

VC

VC

MS

RS RS MS Tandem Connection Path

RS

MS

RS : Regenerator Section MS: Multiplex Section

B3 monitor

B3 monitor

Error count
N1 byte in VC

Error detection (for all VCs in a bundle)

Compare

Data link (for the first VC in the bundle)

Error in TC

* The Tandem Connection is applicable to a single VC or bundled VCs.

40

Functions of POH (VC-1x, VC-2)

V5

Path error monitor Path status report

(V5) (V5)

J2

125s

BIP-2 REI (Remote Error Indication) count of error (BIP-2 results) RFI (Remote Failure Indication) RDI (Remote Defect Indication) receiving path AIS, signal failure indication of VC composition unequipped, equipped-non-specific, asynchronous, bit synchronous, byte synchronous, equipped-unused verification of VC connection user programmable, 15 characters for tandem connection maintenance automatic protection switching at the lower order path level
former FEBE (Far End Block Error) former FERF (Far End Receive Failure) formerly this bit was assigned to Path Trace

Signal label

(V5)

VC-1x / VC-2

N2

Path access point identifier

(J2)

Network operator byte APS signaling

K4

(N2) (K4)

BIP-2
1 2 3

REI
4

RFI
5

Signal Label
6 7

RDI
8

500s

V5 byte

REI ; RDI ; RFI ;

41

Table for SAPI & API

CRC of previous 16 multiframe for J1

maximum 15 characters
(Space) ! # $ & % ( ) * + , . / 0 1 2 (Comma) (Hyphen) (Period) (Apostrophe) 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E

(ex. Tokyo-Osaka #21)

1 C1 C2 C3 C4 C5 C6 C7 J1

F G H I J K L (Colon) (Semicolon) M N O P Q R S T U V W X

Y Z [ \ ] ^ _ (Under Bar) ! a b c d e f g h i j k

l m n o p q r s t u v w x y z { | } ~
example : VC-4 or VC-3 case Total 94 characters plus space 0 x x x x x x x (2) 0 x x x x x x x (1) J1 0 x x x x x x x (#) J1 0 x x x x x x x (k) J1 0 x x x x x x x (T) 0 x x x x x x x (o) J1

125s

J1

J1

2ms

16 multi-frame

42

End-to-End Maintenance Signal

Low Order Path Section High Order Path Section Multiplex Section Regenerator Section LOVC HOVC LT LOS LOF REG LOS LOF AIS RDI (FERF) Regenerator Section LT LOP AIS AIS RDI (FERF) BIP-8 BIP-24N REI (FEBE) BIP-8 RDI (FERF) HOVC LOP AIS AIS AIS LOVC

BIP-8

BIP-2

REI (FEBE)

REI (FEBE) MUX Terminal Equipment generation detection

43

Mapping 2M Signal into VC-12

V5 R V5 R V5 R TS0 TS1 to 15 TS16 TS17 to 31 R J2 R TS0 TS1 to 15 TS16 TS17 to 31 TS 0 R N2 R TS0 TS1 to 15 TS16 TS17 to 31 R K4 R TS0 TS1 to 15 TS16 TS17 to 31 R Byte Synchronous * The latest recommendation deleted bit synchronous mapping. 32 bytes 32 bytes

R J2 C1C2O O O O R R 35 bytes 125 s

R J2 10OOOORR 32 bytes

32 bytes 140 bytes 500 s

R N2 C1 C2 O O O O R R

R N2 10OOOORR

32 bytes

32 bytes

R K4 C1 C2 R R R R R S1 S2 I I I I I I I 31 bytes + 7 bits R Asynchronous

R K4 10RRRRRR 32 bytes

I ; O; C; S; R;

information overhead justification control justification opportunity fixed stuff

R Bit Synchronous

44

Mapping 34M Signal into VC-3

J1 B3 C2 G1 F2 H4 Z3 K3 Z5 T1 3 rows

T2

3 rows

T3 84 bytes VC-3 POH

3 rows 125s

R C 1 , C2 S 1, S 2 I

: : : :

Fixed stu ffing bit Justification control bit Justification opportunity bit Information bit

3x 8 I 3x 8 I 3x 8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

C 3x8 I C 3x8 I C 3x8 I

3x8 I 3x8 I 3x8 I

3x 8 I 3x 8 I 3x 8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I 3x8 I 3x8 I

3x8 I C 3x8 I 3x8 I C 3x8 I 3x8 I A B8 I

=R RR RR RR R

= R R R R R R C1 C2

AB

= R R R R R R R S 1 S2 I I I I I I

45

Mapping 140M Signal into VC-4

STM-1 SOH PTR SOH J1 B3 C2 G1 F2 H4 F3 K3 N1 POH 1 1 12 bytes 96 I X 96 I Y 96 I Y 96 I Y 96 I 20 blocks of 3 bytes 1 byte 13 bytes VC-4

I O C S R

; ; ; ; ;

inform ation overhead justification control justification opportunity fixed stuff

W X Y Z

= = = =

I I I I I I I I C R R R R R OO R R R R R RRR I I I I I I SR

POH W

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

46

Mapping ATM Cell Into VC-4

VC-4

J1 B3 C2 G1 F2 H4 F3 K3 N1
VC-4 POH

header
ATM cell
53 bytes

47

VC-12 (2 Mb/s) to VC-4 (STM-1)

27 0 = 2 61 + 9 SOH

STM-1

AU PTR SOH

125 s
9

AU-4

AU PTR

125 s
26 1 = 86 x 3 + 3
PTR

VC-4
x3

P 9 O S S H

(NPI)

1 2 3 1 2 3 1 2 3 1

1 2 3 125 s

86 = 12 x 7 + 2

TUG-3
x7

N P I

PTR

S S 1 2

(1) 7 1 2

(2) 7 1 2

(3) 7

(4) ~ (11) 7 1 2

(12) 7

125 s
12 = 4 x 3
P TR

TUG-2
x3

V1
9
1 2 3 1 2 3 1 2 3 1 2 3 36

125 s

V2

125 s
36

4
PTR

V3 36

TU-12

VC 12

125 s

36 500 s

48

Mapping of VC-12 into VC-4

49

VC-3 (34 Mb/s) to VC-4 (STM-1)

50

Scrambler
data +
D Q C S D Q C S D Q C S D Q C S D Q C S D Q C S D Q C S

clock set = frame pulse

+

scrambled data
scrambler output not scrambled scrambled

modulo 2 addition
A + B = 1 1 0 0 + 1 = + 0 = + 1 = + 0 = C 0 1 1 0

1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0

1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1

1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1

1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 . . .

1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0

1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0

1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 . . .

1 2 3 . . . . . 9

1111111000000100 - - - -

SOH

Payload Pay l oad

1111111000000100 - - - -

51

2M PDH Signal Extraction from STM-1

9 bytes 9 H1* * H2 * * H3 * * Rows 261 bytes AU PTR
J1

P VC-4 O S S H

(NPI)

261=86x3+3 PTR

4 bytes
V1 V1

123123123
86=12x7+2

123

9 Row
V2

1 36 2 35

V5

9 H1* * H2 * * H3 * * Rows

J1

N P I

PTR S

9 Row V5

34
V2 V5 J2

TUG-3

(1)
12 71 2

(2)
71 2

(3)
71

(4) ~ (11)

(12)
712 7

9 Row

V3

C-12

36 3 144 TS 4 36

35 140 TS 35
K4 N2

9 H1* * H2 * * H3 * * Rows

12=4x3
J1

PTR

V4

V3

TUG-2

9 Row TU-124 Multiframes (4x9 Frame)

2.048Mbit/s Information

12 3 12 3 12 312 3
9 H1* * H2 * * H3 * * Rows
J1

4
4 TU-12
PTR

V4

35

VC-12
TU-12 (4x9 frame)

36 VC-12 4 Multiframes

STM-1 Frame

TU-12 frame in a row

52

Contiguous & Virtual Concatenation

NE-A STM-16
AU-4#1 STM-1

NE-B STM-1
AU-4#1 AU-4#2 AU-4#3 AU-4#4

NE-C STM-16
STM-1

NE-D

STM-4

AU-4#2 AU-4#3 AU-4#4

AU-4#1

STM-4c

VC-4-4c AU-4-4c

AU-4#2 AU-4#3 AU-4#4

AU-4-4c

Contiguous Concatenation

Virtual Concatenation

Contiguous Concatenation

53

Virtual Concatenation
For the transport of payloads that do not fit efficiently into the standard set of virtual containers (VC-3/4/12) VC concatenation can be used. VC concatenation is defined for:
VC-3/4- to provide transport for payloads requiring greater capacity than one Container-3/4; VC-12- to provide transport for payloads that require capacity greater than one Container-12.

54

Contiguous Concatenation of X VC-4s

(VC-4-Xc, X=4, 16, 64, 256)
261X 261X 261N 261N

9X 3 1 RSOH AU-4-4c PTRs

9N 3 1 RSOH AU-4-4 PTRs

1
J1 B3 C2 G1 F2 H4 F3 K3 N1

1
J1 B3 C2 G1 F2 H4 F3 K3 N1

N
J1 B3 C2 G1 F2 H4 F3 K3 N1

MSOH

Fixed Stuff

C-4-Xc

MSOH

C-4-N

STM-N VC-4 POH

STM-N X-1 VC-4-Xc VC-4 POH

VC-4-N

VC-4 POH

Concatenated VC-4-Xc

VC-4-N

55

AU-4 Pointer and Concatenation Indication

a) Nine AU-4 pointer bytes

H1

Y H1

1*

1*

H2

H3 H2

H3

H3

b) Normal AU-4 pointer c) Concatenation indication

N N N N S S I D I D I D I D I D 1 0 0 1 U U 1 1 1 1 1 1 1 1 1 1

(H1, H2) = AU-4 pointer, H3= pointer action byte , Y=(100UU11) U=Unspecified, 1*=(11111111) N = New data flag bit, S= size bit, I= increment bit, D= decrement bit, U=Unspecified

56

Virtual concatenation of X VC-3/4s

(VC-3/4-Xv, X=1.256)
a) VC-3-Xv Structure
1 1 X X x 84 1

b) VC-4-Xv Structure
1 X X x 260

C-3-#X

C-4-#X

125s
1 1 J1 B3 C2 G1 F2 H4 F3 K3 9 N1 85 85

125s
1 1 J1 B3 C2 G1 F2 H4 F3 K3 9 N1 261 261

1 1 J1 B3 C2 G1 F2 H4 F3 K3 9 N1

VC-3-Xc 125s VC-3#X 125s VC-3#1

1 1 J1 B3 C2 G1 F2 H4 F3 K3 9 N1

VC-4-Xc 125s VC-4#X 125s VC-4#1

57

Virtual Concatenation Multiframe Structure

a) Mulltiframe indicator MFI1 Configuration (from Frame 0 to 15)
No used Bit No in H4 MFI X

b) Mulltiframe indicator MFI2 ( from Frame 0 to 255)

MFI2(MSB) MFI2(LSB)

4
0 1 2

5
0 0 0 1 1

6
0 0 0 1 1

7
0 0 1 1 1

8
0 1 0 0 1

Bit No in H4 Frame Frame Frame Frame Frame Frame Frame Frame 0 1 2 126 127 128 129 130

1
0 0 0 0 0 1 1 1 1 1

2
0 0 0 1 1 0 0 0 1 1

3
0 0 0 1 1 0 0 0 1 1

4
0 0 0 1 1 0 0 0 1 1

5
0 0 0 1 1 0 0 0 1 1

6
0 0 0 1 1 0 0 0 1 1

7
0 1 1 1 1 0 0 0 1 1

8
1 0 1 0 1 0 0 0 0 1 Sequencce indiccator SQ LSB (bit 5-8)

Frame Frame Frame

Frame 14 Frame 15

Frame 254 Frame 255

Sequencce indiccator SQ MSB (bit 1-4)

58

VC-3/VC-4-Xv multiframe and sequence indicator

1 C-4/3-Xc X C-4/3-Xc

POH POH POH POH

MFI1:15 MFI1:15

POH

POH

MFI1:0 MF12_MSB:0 MFI1:0 MF12_MSB:0 MFI1:1 MF12_LSB:1 MFI1:1 MF12_LSB:1 SQ:X-1

POH

POH

SQ:0
59

POH

Multiframe (MF)

MFI1:0 MF12_MSB:0 MFI1:0 MF12_MSB:0 MFI1:1 MF12_LSB:0 MFI1:1 MF12_LSB:0

POH

1 1 2 3 4

VC-12-Xv Structure
C-12#Xc

X34

500s

1 1 V5 2 J2 3 N2 4 K4

1 1 V5 2 J2 3 N2 4 K4

35 35 VC-12#Xv 500s VC-12#X 500s

VC-12#1
60

Capacity of virtually concatenated VC-12-Xv

If carried in VC-12-Xv VC-12-Xv VC-12-Xv VC-3 VC-4 Unspecified

Capacity

In steps of 2176 kbit/s 2176 kbit/s 2176 kbit/s

1 to 21 2176 kbit/s to 45 696 kbit/s 1 to 63 2176 kbit/s to 137 088 kbit/s 1 to 64 2176 kbit/s to 139 264 kbit/s

61

VC12 Extended Signal label byte coding

-in K4 bit 11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

0 1 1 1 1 1 1 1 1 1 0
MFAS Extended Signal Label MSB LSB

0 R R R R R R R R R R R R
MFAS: Multiframe Alignment Signal 0: Zero R: Reserved bit

MSB
b12 b13 b14 b15

LSB
b16 b17 b18 b19

Hex code 00 07 08 09 0A 0B 0C 0D FF Reserved

Interpretation

0000 0000 0000 0000 0000 0000 0000 0000 1111

0000 0111 1000 1001 1010 1011 1100 1101 1111

Mapping under development ATM mapping Mapping of HDLC/PPP framed signal Mapping of HDLC/LAPS framed signals Virtually concatenated test signal, O.181 specific mapping Flexible Topology Data Link mapping Reserved

62

K4 bit 2 multiframe:K4 (b2)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Frame count Sequence indicator

RRRRRRRRRRRRRRRRRRRRR R: Reserved bit

63

64

65

Review Questions
Fill up the spaces enclosed in parentheses in the following sentences with correct words. 1. B1 is to monitor a ( a ) error and B2 is for monitor a ( b ) error. For STM-4, the monitoring method of B1 is ( c ) and the monitoring method of B2 is ( d ). 2. K1 and K2 are called ( a ) signaling and used to exchange of transfer control information among nodes in an ( b ) Ring and a ( c ) protection ( d ) system. 3. M1 is used to report a result of error detection by ( a ) , by number of ( b ) violation. 4. G1 is used to report the receiving status of ( a ) back to the ( b ) side. 5. H4 is used to display a ( a ) number in a multiframe required to process the TU pointer. 6. ( a ) 2,048 kb/s signal is required in frequency justification between ( b ) and SDH is necessary. ( c ) synchronous 2,048 kb/s signal is always ( d ) bit is used and ( e ) bit is not used. To indicate this status ( f ) and ( g ) are always set to 1 and 0 automatically. ( h ) synchronous 2,048 kb/s signal location of 64 kb/s channels of 2M in VC-12 is allocated 7. SDH pointers require 10 bits (5 Is and 5 Ds) of pointer value because of the maximum possible pointer offset value of AU-4 pointer is ( a )

66