1

Lecture 1: Introduction to
Microprocessors and Microcomputers
Seungryoul Maeng
Computer Science, KAIST
Fall 2000
Maeng
Lect01-2
Syllabus

Course ra!ing"
#
" $0 %

" 2&%

" 2&%

' , ( " 10%

# " &
!
#
" " )0%

Course Te*ts"
1+ T,e -0.-$, -0)-$, an! /entium /rocessor, 0alter A+ Trie1el,
/rentice 2all+
2+ " #$
Maeng
Lect01-.
Syllabus

%
#
& '(, 3oom .).-, maeng4cs+5aist+ac+5r
#
,ome page " ,ttp"66camars+5aist+ac+5r67maeng
#
899ice 2ours " Mon, 0e!+ 1."00 - 1)".0

TAs
#
)*

Course :escription

"
#
2 + ,- .
Maeng
Lect01-)
What is a microcomputer system?

;loc5 !iagram o9 a !igital computer

;loc5 !iagram o9 a microcomputer system

Memory
Input
C/<
8utput
Memory
Input
Microprocessor
8utput
Maeng
Lect01-&
NMOS Inverter
=M8S Transistor'=M8S F>T(
S
i
O
2
( 0.6 micron)
P type silicon
gate oxide( 0.05 micron)
polysilicon(Low Pressure Cemical
!apor "eposition )
#
S

Source$ drain
n% n%
Maeng
Lect01-$
NMOS Inverter

n% n%


n% n%
contact
aluminum $
2
Lengt unit &&&
(micron)

aluminum
Maeng
Lect01-?
What is a microprocessor?

Criteria
#
num1er o9 c,ips
#
!ata pat,
#
a!!ress space
#
C/< per9ormance
#
/rice

Types o9 microprocessor
#
Application

3e-programma1le microprocessors

em1e!!e! microprocessors an! micro-controllers

#
Instruction comple*ity

CISC

3ISC
Maeng
Lect01--
Classes of Computers

0,at is t,e !i99erence 1et@een main, mini, an! microA

#
T,e capacity an! per9ormance o9 t,e electronics use! to
implement t,eir 1uil!ing 1loc5s an! t,e resulting oBerall system
capacity an! per9ormance+

C/< per9ormance
[ ] [ ] n instructio per cycles cloc5 !elays pac5age logic o9 leBels e s@itc, tim circuit
1
+
= MIPS
Tec, :riBen
Mac,ine
8rganiCation
Maeng
Lect01-D
Microprocessor Architecture /

!i99erent 9rom t,e arc,itectures o9 large main 9ramesA

0,yA

8ne or a 9e@ ELSI c,ips

ELSI enBironments
#
!ensity per c,ip

!ie siCe ---- yiel!

9eature siCe --- 1+0 micron, 0+. micron

#
I68 pa!

c,ip cost

po@er consumption

propagation !elay
Maeng
Lect01-10
The istory of Intel!s Microprocessors

Intel )00)
#
1D?1, )-1it

Intel -00-
#
1D?2, --1it
#
8riginally !esigne! 9or :atapoint Corp+ as a C3T !isplay
controller

Intel -0-0
#
1D?), April - Altair --00, 1D?&, MITS' 2&$ 1ytes o9 Mem, F.D&(
#
Apple II -- SteBe Go1s an! SteBe 0oCnia5 1D?$, Apple 01
#
;ill ates an! a 9ello@ stu!ent " ;ASIC, 1D?& --H Microso9t

Intel -0-$6-0--
#
1D?-, 1$ 1it" -0--, 1D?D, --1it e*ternal 1us
Maeng
Lect01-11
The istory of Intel!s Microprocessors
#
I;M /C I 1D-1
#
2D,000 Trs

Intel -02-$
#
1D-2, 1$-1it arc,itecture
#
2)-1it a!!ressing, memory protection an! Birtual memory
#
1$ M; o9 p,ysical M>M an! 1 ; o9 Birtual mem
#
1.0,000 Trs onto a single c,ip
#
I;M /C6AT in 1D-), I;M /S62 Mo!el &0 an! $0

Intel -0.-$
#
1D-&, .2 1its
#
.7& MI/S '? MI/S on t,e 2& M2C c,ip(
#
memory paging an! en,ance! I68 permission 9eatures
#
); programming mo!el
Maeng
Lect01-12
The istory of Intel!s Microprocessors

Intel -0)-$
#
1D-D Spring C8M:>J s,o@ -H 1DD0 Gune " actual release
#
1,200,000 Trs
#
.-$K.-?K-K !ata an! instruction cac,e, paging an! MM<

/entium
#
1DD.
#
110 MI/S on $$ M,C C,ip
#
1$ K; on-c,ip cac,e an! $) 1it !ata 1us
#
superscalar tec,nology 't@o instructions6cloc5(
#
.+1 million transistors
Maeng
Lect01-1.
The istory of Intel!s Microprocessors

/entium /ro
#
1DD&, Superscalar't,ree-@ay issue(
#
&+& million Trs in t,e C/< core K 1&+& million Trs in t,e
secon!ary cac,e -K !ata, -K instr cac,e
#
2&$ K; S3AM secon!ary cac,e
#
200 S/>CintD2 at 1.. M2C
#
2+D E, 0+$ micron ;ICM8S

/entium II
#
/entium /ro K MMJ, 1DD?
#
2.., 2$$, upto )&0 M2C
#
?+& million Trs in C/<
#
&12K; in secon!ary cac,e
Maeng
Lect01-1)

/entium III
#
1DDD
#
/entium /ro K MMJ K Internet Streaming SIM: Instructions
#
0+2& micron, D+& million Trs
#
$00 M2C, &&0 M2C,+++
#
.2 K'1$K61$K( non-1loc5ing leBel 1 cac,e
The istory of Intel!s Microprocessors
15
I"M PC#AT and ISA "us
Maeng
Lect01-1$
$%&$'(based PC#AT(Compatible System
L
8
C
A
L

;
<
S
S
L
S
T
>
M

;
<
S
.-$:J
.-? :J
-2.-&:J
Cac,e
Controller
Cac,e
;I8S
In!ustry Stan!ar! Arc,itecture'ISA( ;us
-2.)&
:ata
;u99er
-2.)$
System
Controller
-2.))
ISA
Controller
:3AM
-2.)1
/erip,eral
Com1o
386DX+82340 chip set
Maeng
Lect01-1?
Pentium Processor#$)*&% PCIset ISA
/entium /rocessor Host Bus
C=TL
A::3
:ATA
S3AM
Latc,
C=TL
A::36:ATA
PCI BUS
ISA BUS
-2).)
/CMC
:3AM
-2)..
L;J
-2.?- SI8 rap,ics /CI !eBices
Maeng
Lect01-1-
ISA "us Interface Si+nals
P i n N!" #$%" P i n N!" #$%"
&' ( )* +, +-. ( /' 0N1
&2 13 ( )* /2 4565# 147 *
&8 19 ( )* /8 :;7
&< 1; ( )* /< ( 4=2 (
&; 1< ( )* /; >;7
&9 18 ( )* /9 14=2 (
&3 12 ( )* /3 >'27
&? 1' ( )* /? 45654751
&@ 1A ( )* /@ :'27
&'A ( )* +, 41B ( /'A 0N1
&'' &5N * /'' 6C5CD. *
&'2 &'@ * /'2 6C5C4. *
&'8 &'? * /'8 ( *D. *
&'< &'3 * /'< ( *4. *
&'; &'9 * /'; 1&+-8. *
&'9 &'; * /'9 14=8 (
&'3 &'< * /'3 1&+-'. *
&'? &'8 * /'? 14=' (
&'@ &'2 * /'@ 45E456,. *
&2A &'' * /2A +F*+- *
&2' &'A * /2' ( 4=3 (
&22 &@ * /22 ( 4=9 (
&28 &? * /28 ( 4=; (
&2< &3 * /2< ( 4=< (
&2; &9 * /2; ( 4=8 (
&29 &; * /29 1&+-2. *
&23 &< * /23 #)+ *
&2? &8 * /2? /&F5 *
&2@ &2 * /2@ :;7
&8A &' * /8A *6+ *
Maeng
Lect01-1D
ISA "us Interface Si+nals
P i n N!" #$%" P i n N!" #$%"
+' 6/,5. * 1' C5C +6 '9 . (
+2 F&28 * 12 ( * +6 '9. (
+8 F&22 * 18 ( 4='A (
+< F&2' * 1< ( 4='' (
+; F&2A * 1; ( 4='2 (
+9 F&'@ * 19 ( 4='8 (
+3 F&'? * 13 ( 4='< (
+? F&'3 * 1? 1&+-A. *
+@ C5C4. * 1@ 14=A (
+'A C5CD. * 1'A 1&+-;. *
+'' 61A? ( )* 1'' 14=; (
+'2 61A@ ( )* 1'2 1&+-9. *
+'8 61'A ( )* 1'8 14=9 (
+'< 61'' ( )* 1'< 1&+-3. *
+'; 61'2 ( )* 1'; 14=3 (
+'9 61'8 ( )* 1'9 :;7
+'3 61'< ( )* 1'3 C&6#54. (
+'? 61'; ( )* 1'? 0N1
Maeng
Lect01-20
"loc, -ia+ram of the System "oard
All signal lines are TTL compati1le+ Fan-out are t@o lo@ po@er S,ott5ey'LS( TTLs+
SA0 t,roug, SA1D" System A!!ress ;us"'I68(
# to a!!ress memory an! I68 !eBicesI 1$M; o9 memory @it, LA1? t,roug, LA2.
# input @,en C/<2L:A is ,ig, an! MAST>3M is lo@I output at all ot,er times
# SA 1us !riBen 1y C/< @,en C/<2L:A is lo@I SA 1us !riBen 1y -2.? :MA controller @,en
C/<2L:A is ,ig,
# latc,e! @it, an internally generate! AL> signal
I
S
A

;
u
s
C
/
<
!
a
t
a
a
!
!
r
:MA M>M
!ata
a!!r
>*ternal
Master
Memory
I68
Maeng
Lect01-21
LA1? t,roug, LA2. 'Latc,a1le A!!ress ;us(I I68
# t,e same as SA1D-SA0
M>M3M 'Memory 3ea!, actiBe lo@(I I68
# Input @,en C/<2L:A is ,ig, an! MAST>3M is lo@
# it is !riBen 9rom t,e 2-- 1us controller @,en C/<2L:A is lo@ an! MAST>3M is ,ig,
# it is !riBen 1y t,e -2.? :MA controller @,en C/<2L:A is ,ig, an! MAST>3M is ,ig,
# reNuires an e*ternal 10K pull-up resistor
M>M0M'Memory 0rite, actiBe lo@(" I68
# Input6output !etermination" t,e same as M>M3M
# reNuires an e*ternal 10K pull-up resistor
SM>M3M'Memory 3ea!(" I68
# Input68utput !etermination" t,e same as M>M3M
# actiBe on memory rea! cycles to a!!resses 1elo@ 1 M;+
#
reNuires an e*ternal 10K pull-up resistor
SM>M0M'Memory 0rite("I68
# Input68utput !etermination" t,e same as M>M3M
# actiBe on memory rea! cycles to a!!resses 1elo@ 1 M;+
# reNuires an e*ternal 10K pull-up resistor
S;2>M'System ;yte 2ig, >na1le( " I68
# controlle! t,e same @ay as t,e SA 1us
Maeng
Lect01-22
3>F3>S2M'3e9res, signal(I I68
SLSCLK'System Cloc5( " 8
# t,is output is ,al9 t,e 9reNuency o9 t,e ;<SCLK input
# ;AL>, I83M, I80M, M>M3M, M>M0M are sync,roniCe! to SLSCLK
8SC'8scillator(" I-TTL
# t,e 1u99ere! in6out o9 t,e e*ternal 1)+.1- M2C oscillator+
3ST:3E'3eset :riBe(" 8
;AL>';u99ere! A!!ress Latc, >na1le(" 8
# A pulse @,ic, is generate! at t,e 1eginning o9 any 1us cycle initiate! 9rom t,e C/<+
A>= 'A!!ress >na1le(" 8
# goes ,ig, anytime t,e inputs C/<2L:A an! MAST>3M are 1ot, ,ig,
# :MA controller ,as control @,en t,is signal is actiBe
T6C 'Terminal Count(" 8
# in!icates t,at one o9 t,e :MA c,annels terminal count ,as 1een reac,e!
:ACK?M- :ACK&M, :ACK.M- :ACK0M ':MA Ac5no@le!ge(" 8
:3O?-:3O&, :3O.-:3O0 ':MA 3eNuest( " I
# :3O0-:3O. " 9rom --1it I68 a!apters to69rom system memory
# :3O&-:3O?" 9rom 1$-1it I68 to69rom system memory
# :3O) is not aBaila1le e*ternally as it is use! to casca!e t,e t@o :MA controllers toget,er+
Maeng
Lect01-2.
I3O1&-I3OD, I3O?-I3O., I3O1 'Interrupt 3eNuest( " I
# inputs 9or t,e -2&D megacells
# I3O0, I3O2, I3O- I not aBaila1le as e*ternal inputs
MAST>3M 'Master( " I
# use! 1y an e*ternal !eBice to !isa1le t,e internal :MA controllers an! get access to t,e system
1us
# @,en asserte! it in!icates t,at an e*ternal 1us master ,as control o9 t,e 1us+
M>MCS1$M 'Memory C,ip Select 1$-1it( " I
# use! to !etermine @,en a 1$-1it to --1it conBersion is nee!e! 9or C/< a!!resses
# A 1$ to - conBersion is !one anytime t,e System Controller reNuests a 1$-1it memory cycle
an! MAST>3M is sample! ,ig,+
I8CS1$M 'I68 C,ip Select 1$-1it( " I
# 9unctions t,e same @ay as M>MCS1$M signals
I8C2KM 'I68 C,annel C,ec5(" I
# use! to in!icate t,at an error ,as ta5en place on t,e I68 1us
I8C23:L 'I68 C,annel 3ea!y( " I
# pulle! lo@ in or!er to e*ten! t,e rea! or @rite cycles o9 any 1us access @,en reNuire!
# t,e !e9ault num1er o9 @ait states 9or cycles initiate! 1y t,e C/<I
9our @ait states 9or --1it perip,erals
one @ait state 9or 1$-1it perip,erals
t,ree @ait states 9or 38M cycles
# 8ne @ait state is inserte! as t,e !e9ault 9or all :MA cycles
Maeng
Lect01-2)
0S0M '0ait State 0( " I
# pulle! lo@ 1y a perip,eral on t,e 1us to terminate a C/< controlle! 1us cycle earlier t,an t,e
!e9ault Balues