Submicron Cmos Technology: Mary Brigit Asha A A S1 Mtech Ece
Submicron Cmos Technology: Mary Brigit Asha A A S1 Mtech Ece
Submicron Cmos Technology: Mary Brigit Asha A A S1 Mtech Ece
TECHNOLOGY
Mary Brigit Asha A A
S1 MTECH ECE
1
INTRODUCTION
Rapid pace of improvement in
semiconductor industry =>scaling
down device dimension
Speed and no. of transistors/unit area
Scaling of lateral and vertical
dimensions
2
Categorization of CMOS Technology
Minimum feature size as a function of
time:
3
Categories of CMOS technology:
1.) Submicron technology Lmin >= 0.35
microns
2.) Deep Submicron technology (DSM)
0.1 microns <= Lmin <=0.35 microns
3.) Ultra-Deep Submicron technology (UDSM)
Lmin <= 0.1 microns
4
TYPICAL SUBMICRON CMOS FABRICATION
PROCESS
N-Well CMOS Fabrication
Step 1 - Implantation and diffusion of the n-wells
Step 2 - Growth of thin oxide and deposition of silicon
nitride
5
Step 3.) Implantation of the n-type field channel stop
channel-stop :
-produced by implantation or diffusion of ions, by growing
or patterning the silicon oxide
-primary function to limit the spread of the channel area or
to prevent the formation of parasitic channels
6
Step 4.) Implantation of the p-type field
channel stop
Step 5.) Growth of the thick field oxide
(LOCOS - localized oxidation of silicon)
7
Step 6.) Growth of the gate thin oxide and
deposition of polysilicon.
The thresholds can be shifted by an implantation before the
deposition of polysilicon.
8
Step 7.) Removal of polysilicon and
formation of the sidewall spacers
9
Step 8.) Implantation of NMOS source
and drain
Step 9.) Remove sidewall spacers and
implant the NMOS lightly doped
source/drains
10
Step 10.) Implant the PMOS source/drains
and contacts to the p- substrate (not
shown), remove the sidewall spacers and
implant the PMOS lightly doped
source/drains
11
Step 11.) Anneal to activate the
implanted ions
12
Step 12.) Deposit a thick oxide layer
(BPSG - borophosphosilicate glass)
Step 13.) Open contacts, deposit first level
metal and etch unwanted metal
13
Step 14.) Deposit another interlayer
dielectric (CVD SiO2), open
contacts,deposit second level metal
14
Step 15.) Etch unwanted metal and
deposit a passivation layer
15
16
Submicron MOSFET Cross-section
17
18
TEM micrograph of physical structure of sub-micron
gate and metal interconnects
19
20
Isolation of Transistors
Reverse biased pn junctions to isolate
transistors becomes impractical as the
transistor sizes decrease.