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    Different Types of ASIC

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    Parth Shah
    This document provides an introduction and overview of different types of ASICs (Application Specific Integrated Circuits), including full custom ASICs, semi-custom ASICs, and different varieties of semi-custom ASICs. Standard cell based ASICs use pre-designed logic cells that can be placed anywhere, while gate array based ASICs have predefined transistors with customizable interconnect layers. Channelized gate arrays have fixed interconnect spaces, while channelless and structured gate arrays allow more flexible interconnect routing. Full custom ASICs are the most application specific but have the longest design time.

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    Different Types of ASIC

    Uploaded by

    Parth Shah
    1K views21 pages
    This document provides an introduction and overview of different types of ASICs (Application Specific Integrated Circuits), including full custom ASICs, semi-custom ASICs, and different varieties of semi-custom ASICs. Standard cell based ASICs use pre-designed logic cells that can be placed anywhere, while gate array based ASICs have predefined transistors with customizable interconnect layers. Channelized gate arrays have fixed interconnect spaces, while channelless and structured gate arrays allow more flexible interconnect routing. Full custom ASICs are the most application specific but have the longest design time.

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    Presentation is useful for learning types of ASIC

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    This document provides an introduction and overview of different types of ASICs (Application Specific Integrated Circuits), including full custom ASICs, semi-custom ASICs, and different varieties of semi-custom ASICs. Standard cell based ASICs use pre-designed logic cells that can be placed anywhere, while gate array based ASICs have predefined transistors with customizable interconnect layers. Channelized gate arrays have fixed interconnect spaces, while channelless and structured gate arrays allow more flexible interconnect routing. Full custom ASICs are the most application specific but have the longest design time.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    1K views21 pages

    Different Types of ASIC

    Uploaded by

    Parth Shah
    This document provides an introduction and overview of different types of ASICs (Application Specific Integrated Circuits), including full custom ASICs, semi-custom ASICs, and different varieties of semi-custom ASICs. Standard cell based ASICs use pre-designed logic cells that can be placed anywhere, while gate array based ASICs have predefined transistors with customizable interconnect layers. Channelized gate arrays have fixed interconnect spaces, while channelless and structured gate arrays allow more flexible interconnect routing. Full custom ASICs are the most application specific but have the longest design time.

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    INTRODUCTION TO ASIC

    DESIGN

    Types of ASIC

    Full custom ASIC


    A full-custom IC includes some (possibly all) logic cells that are customized
    and all mask layers that are customized.
    A microprocessor is an example of a full-custom ICdesigners spend many
    hours squeezing the most out of every last square micron of microprocessor
    chip space by hand.
    Customizing all of the IC features in this way allows designers to include
    analog circuits, optimized memory cells, for example. Full-custom ICs are
    the most expensive to manufacture and to design.
    The manufacturing lead time (the time it takes just to make an ICnot
    including design time) is typically eight weeks for a full-custom IC.
    These specialized full-custom ICs are often intended for a specific application so, we might
    call some of them as full-custom ASICs.

    Full custom ASIC


    Advantage
    Accuracy
    Disadvantage
    More time to market

    SEMI CUSTOM ASICs


    ASICs , for which all of the logic cells are predesigned and some (possibly all) of
    the mask layers are customized are called semi custom ASICs.
    Using the predesigned cells from a cell library makes the design ,
    much easier.
    There are two types of semicustom ASICs
    1. Standard cell based
    2. Gate array based

    Standard-Cell Based ASICs


    A cell-based ASIC (CBIC) uses predesigned logic cells
    (AND gates, OR gates, multiplexers, and flip-flops, for
    example) known as standard cells.
    One can apply the term CBIC to any IC that uses cells, but it is
    generally accepted that a cell-based ASIC or CBIC means a standardcell based ASIC.

    Standard-Cell Based ASICs.


    The standard-cell areas (also called flexible blocks) in a CBIC are
    built of rows of standard cells like a wall built of bricks. The standardcell areas may be used in combination with microcontrollers or even
    microprocessors, known as mega cells. Mega cells are also called
    mega functions, full-custom blocks, system-level macros (SLMs),
    fixed blocks, cores, or Functional Standard Blocks (FSBs).

    Standard-Cell Based ASICs.


    A cell-based ASIC (CBIC) die with a single standard-cell area (a flexible block) together with four fixed
    blocks.

    Standard-Cell Based ASICs.


    The ASIC designer defines only the placement of the standard cells
    and the interconnect in a CBIC. However, the standard cells can be
    placed anywhere on the silicon; this means that all the mask layers of a
    CBIC are customized and are unique to a particular customer.

    Standard-Cell Based ASICs.


    Each standard cell in the library is constructed using full-custom
    design methods, but you can use these predesigned and pre
    characterized circuits without having to do any full-custom design
    yourself.
    This design style gives you the same performance and flexibility
    advantages of a full-custom ASIC but reduces design time and
    reduces risk.
    The disadvantages are the time or expense of designing or buying the standardcell library and the time needed to fabricate all layers of the ASIC for each new
    design.

    Gate-Array Based ASICs


    In a gate array (sometimes abbreviated GA) or gate-array based ASIC the
    transistors are predefined on the silicon wafer.
    The predefined pattern of transistors on a gate array is the base array , and the
    smallest element that is replicated to make the base array is the base cell
    (sometimes called a primitive cell ).
    Only the top few layers of metal, which define the interconnect
    between transistors, are defined by the designer using custom
    masks. To distinguish this type of gate array from other types of
    gate array, it is often called a masked gate array ( MGA ).

    Gate-Array Based ASICs


    There are the following different types of MGA or gate-array
    based ASICs
    1. Channeled gate arrays.
    2. Channelless gate arrays.
    3. Structured gate arrays.

    Channeled gate arrays


    A channeled gate array is similar to a CBIC. Both use the rows of cells
    separated by channels used for interconnect. One difference is that the
    space for interconnect between rows of cells are fixed in height in a
    channeled gate array, whereas the space between rows of cells may be
    adjusted in a CBIC.
    The important features of this type of MGA are
    Only the interconnect is customized.
    The interconnect uses predefined spaces between rows of base cells.
    Manufacturing lead time is between two days and two weeks.

    Channeled gate arrays

    Channel less Gate Array


    This channel less gate-array architecture is now more widely used . The routing on
    a channelless gate array uses rows of unused transistors.
    The key difference between a channel less gate array and channeled gate array is
    that there are no predefined areas set aside for routing between cells on a channel
    less gate array. Instead we route over the top of the gate-array devices. We can do
    this because we customize the contact layer that defines the connections between
    metal 1, the first layer of metal, and the transistors.

    Features of Channel less Gate Array

    Only the interconnect is customized.


    The interconnect uses predefined spaces between rows of base cells.
    Manufacturing lead time is around two days to two weeks.
    When we use an area of transistors for routing in a
    channel less array, we do not make any contacts to the
    devices lying underneath , we simply leave the
    transistors unused.

    A channel less gate-array or sea-of-gates


    (SOG) array die.

    Structured Gate Array

    This design combines some of the features of CBICs and MGAs. It is


    also known as an embedded gate array or structured gate array.
    One of the limitations of the MGA is the fixed gate-array base cell.
    This makes the implementation of memory, difficult and inefficient.
    In an embedded gate array some of the IC area is set aside and
    dedicate it to a specific function. This embedded area either can
    contain a different base cell that is more suitable for building memory
    cells, or it can contain a complete circuit block, such as a
    microcontroller.

    A structured or embedded gate-array die showing


    an embedded block in the upper left corner

    Features of Structured Gate Array


    Only the interconnect is customized.
    Custom blocks (the same for each design) can be embedded.
    Manufacturing lead time is between two days and two weeks.
    An embedded gate array gives the improved area efficiency and
    increased performance of a CBIC but with the lower cost and faster
    turn around of an MGA.
    The disadvantage of an embedded gate array is that the embedded
    function is fixed.

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