A presentation on

Envelope Tracking in Power Amplifiers

under the guidance of

Dr. (Mrs.) Meenakshi Rawat

Assistant Professor, Department of ECE
IIT Roorkee

Presented by

ANURAG VIJAY AGRAWAL

Research Scholar

DEPARTMENT OF ECE , IITR

Outline

Introduction
Transmitter Architectures
Applications Areas
Algorithm Classes
Previous Works
Inferences drawn
Proposed Work Objectives
Design Methodology
Proposed Model Development
Results and Discussions
Conclusion
Future Scope
References

Introduction

Introduction
Now-a-days, more and more wireless services and
applications are being developed in order to eliminate the
wire-link among commercial products such as computers,
digital cameras, video cameras, mobile phones, gaming
devices and digital TVs.
The necessity of high data rates wireless communication
becomes important for the end-user, especially to support
high mobility lifestyle always get connected.

Introduction
Today, there are an increasing number of wireless
communication standards that are employed by wireless
communication devices.

These are operated in a variety of different frequency bands which

can be different from country to country.
In addition, these standards employ different modulation types.

For example, GSM employs Gaussian Minimum Shift

Keying (GMSK), EDGE employs GMSK and 8-Phase Shift
Keying (8-PSK), UMTS employs Code Division Multiple
Access (CDMA), etc.

Introduction
The current wireless communication systems require a
multiband and multimode approach.

so that several communication standards and applications can be

incorporated in one device to satisfy the users.

who expect mobility, ubiquitous connection and high data rates at the same time.

Transmitter Architectures

Transmitter Architectures
The traditional analog I/Q radio architectures
are not well suited to multiband and
multimode operation due to their bandspecific nature.

requiring use of surface acoustic wave (SAW)

bandpass filters.
The

use of SAW filters forces designers to diplex the

signal path or build individual transmitter chains for
each band of interest.

Transmitter Architectures
Fortunately, the true multiband and
multimode operation can be achieved in a
single transmit chain through polar
transmitter architectures.

utilizes envelope and phase components to

represent digital symbols instead of the I/Q
signals.
requirement

of an efficient method for rapid phase and

magnitude extraction.

Transmitter Architectures
An efficient Rectangular to Polar Conversion
(RPC) is always needed by the polar
architectures for wireless communication
systems.
Through this, a polar modulation offers the
capability of achieving high linearity and
high efficiency simultaneously in a wireless
transmitter.

Rectangular to Polar
Conversion
Conventional modulation strategies use orthogonal vectors to describe a twodimensional space. These basis vectors are typically referred to as in-phase, I and
quadrature, Q.
The RF signal trajectory is mapped using I(t) and Q(t) baseband signals and up
converted using quadrature local oscillators :
v(t) = I(t) sin(ct) + Q(t) cos(ct)
The same RF signal trajectory can be decomposed into polar form using the
amplitude and phase of the RF carrier. With a polar representation, the modulated RF
signal follows :
v(t) = A(t)cos[ct +(t)]

Rectangular to Polar
Conversion
In most digital communication systems, the frequency of the
carrier is fixed, so only phase and magnitude need to be
considered. The unmodulated carrier is the phase and
frequency reference, and the modulated signal is interpreted
relative to the carrier.

Rectangular to Polar
Conversion
By forcing the carrier to one of several predetermined positions in the IQ plane, the encoded information can be transmitted.
The mapping of the states or symbols at each symbol timing instant
(when the receiver interprets the signal) on the I-Q plane is referred to as
a constellation diagram.

Rectangular to Polar
Conversion
Advantages

The same modulator can be used to generate a variety of

modulations from digital formats to RF pulses, or even radar
chirps.
Effects like cross talk, data skew, compression, and AM-to-PM
distortion, which are hard to visualize otherwise, are easy to see.

Application Areas
in M-ary phase shift keying receivers.
in GMSK scheme used in GSM technology.
for down-conversion in CDMA and UMTS.
in general wideband PM/FM demodulators.
in digital beam positioning.

Algorithm Classes
LUT-based Algorithms
Polynomial Approximation Algorithms
Rational Approximation Algorithms
Quadratic Convergence Algorithms
Linear Convergence Algorithms

CORDIC Algorithm

CORDIC Algorithm
The key concept of CORDIC arithmetic is
based on the simple and ancient principles of
two-dimensional geometry.
It only needs the use of 2-shifters and 3adders modules, as a result its power
dissipation is very low as compared to other
methods and it is also very compact.

CORDIC Algorithm
The rotation mode is used to perform
the general rotation by a given angle .
The vectoring mode computes unknown
angle of vector by performing a nite
number of micro-rotations.

CORDIC Algorithm
The generalised equations of the CORDIC
algorithm for an iteration can be written as:
xi+1 =
xi p i yi -Sp,i
yi+1

i xi -Sp,i + yi

zi+1

zi i p,i

CORDIC Architectures

Previous Works
Takayuki Tsukizawa et al. in [4] have proposed a 3G/GSM/EDGE
multiband/multimode transceiver architecture that achieves the
elimination of Tx-SAW filter. Sufficient ACLR performance is
accomplished by a combination of parts-to-parts calibration and
temperature offset compensation. The design details and experimental
results have been included in the paper.
Jaimin Mehta et al. in [6] have reported a new linearization scheme, in
which measured amplitude and phase distortions are stored in lookup
tables and used for pre-distortion. The presented linearization system is
part of a polar transmitter that utilizes CORDIC module to convert the
Cartesian form (I,Q) 8PSK constellation information coming from the
pulse-shaping lter into the polar representation (, ).

Previous Works
Georgious Kardaras et al. in [8] have suggested the importance of a DPD
block and an adaptive polynomial approach based on Cartesian to Polar
conversion is then proposed. Such radio architecture has successfully
been implemented on a low-cost FPGA family meeting the WiMAX/LTE
spectrum and Error Vector Magnitude (EVM) requirements.
Shen-Fu Hsiao et al. in [9] have presented multi-stage architectural
design of rectangular-to-polar coordinate conversion (RPC) for digital
communication systems. Given a two-dimensional (2-D) vector, the key
operation in the RPC is to calculate the arctangent value and the vector
length. The RPC operation can be considered as finding a rotation to
align the given vector along the x axis. The paper concluded that for
medium-to-high precision (such as 24-bit and 32-bit), CORDIC-based
architecture has much smaller area at the cost of slightly increased
latency.

Previous Works
C. Berland et al. in [10] stated that EER is an analog solution that relies
upon the separation of the envelope and phase parts of the modulated
signal; and envelope variation in digital modulation increases transmitter
design complexity. This paper presents a new versatile digital transmitter
architecture that can be adopted for any non constant modulation, on a
wide range of frequencies, with high linearity and efficiency.
David D. Hwang et al. discussed in [12] that the efficient conversion of
rectangular to polar coordinates is necessary in many modern
communication applications. The authors implemented a 400 MHz
digital rectangular to polar coordinate converter in 0.25-m CMOS. The
inputs to the chip are 14-bit in-phase and quadrature channels, and the
outputs are 15-bit magnitude and phase channels. The phase and
magnitude calculations have a maximum error of 0.00024 and 0.03,
respectively and at a maximum frequency of 406 MHz, the circuit
dissipates 470 mW of power at 2.5 V.

Previous Works
Pramod Kumar Meher and Sank Yoon Park [16] have suggested that since
the CORDIC algorithm exhibits linear-rate convergence, it requires (n +
1) iterations to have n-bit precision of the output.
B. Lakshmi, and A.S. Dhar in [21] have showed that to have n-bit output
precision, the rectangular-to-polar conversion by the radix-4 CORDIC
algorithm requires n/2 micro-rotations, which is half that of radix-2
algorithm. However, it requires more computation time for each iteration
and involves more hardware compared to the radix-2 type.
Jun Ma et al. in [27] have suggested that as the CORDIC iterations are
identical, it is very much convenient to map them into pipelined
architectures.
O. Sarbishei and K. Radecka [31] have presented that area, and accuracy
CORDIC algorithm depend mainly on the iteration count and its
implementation. The hardware requirement therefore increases
accordingly with the desired accuracy.

Previous Works
Roberto Gutierrez and Javier Valls in their paper [38] have presented
architecture for the computation of the atan(Y/X) operation suitable for
broadband communication applications. The architecture is based on
LUT methods and achieves lower power consumption with respect to an
atan(Y/X) operator based on CORDIC algorithm with a lower latency
but provides low precision and high cost implementation.
A. I. Mecwan and N. P. Gajjar [46] stated that reconfigurability in radio
development is not such a new technique as one might think. Already
during the 1980s reconfigurable receivers were developed for radio
intelligence in the short wave range. The paper suggested that the next
generation of communication will be driven by the technology called
Cognitive Radio that can adapt the environment around it.

Previous Works
R. Gutierrez et al. in [51] presented an architecture for the
computation of the atan(Y/X) operation suitable for broadband
communications systems. A combination of non-uniform
segmentation and multipartite LUT technique is proposed for the
arctangent of the logarithmic approximation. The architecture was
implemented in an XC2V3000-4FG676 Xilinx FPGA device. Area
and maximum working frequency were obtained with the 10.1 Xilinx
ISE tool. The architecture achieved higher throughput than the
approach based on CORDIC algorithm and lower area than
previous LUT-based approaches.
The literature review has been done on three aspects. Firstly, the
transmitter architectures for providing multiband and multimode wireless
communications were investigated, then various algorithms for designing
such architectures were investigated and finally different platforms for
the implementation of suitable architectures were analysed.

Inferences Drawn
For one application, the high speed solution is always a requirement
and for the other, the careful handling of scale factors for high
precision implementations is required.
For high-throughput applications, efficient pipelined-architectures with
multiple- units could be developed to take the advantage of
pipelineability of the existing methods.
Area, accuracy and latency of CORDIC algorithm depend mainly on the
iteration count and its implementation. The hardware requirement
increases accordingly with the desired accuracy. Floating-point
implementation naturally gives higher accuracy than its fixed-point
counterpart, but at the cost of more complex hardware.

Inferences Drawn
The additional accuracy resulting from floating-point implementation or
better angle approximation is also not necessary in many applications.
Thus, there is a need for trade-off between hardware-cost, latency and
numerical accuracy.
To have better angle approximation, more number of iterations are
required which increases the latency.
A low power architecture is also always needed for broadband
communication applications due to which optimum power-efficient
solutions are required for the purpose as modern wireless technology
has opened up a vast range of possibilities with voice, video and data
applications dominating the space with newer multimedia services
everyday.

Problem Definition
Many wireless communication systems require the efficient conversion of
rectangular to polar coordinates.

In previous years, several algorithms and architectures have been developed.

Analysing the ability and potential of the multiplier-less algorithms, like

CORDIC, it is thought to be suitable to work efficiently and effectively for the
Rectangular-to-Polar conversion.
Thus it is observed from the literature survey that most of the work has been done on
providing speed, precision and area- efficient solutions separately and no author is
working on these parameters simultaneously. The research in these areas has been
continuing and there is still a need for developing faster, more precise, utilizing lessarea and low cost solutions by working on these parameters simultaneously.

Proposed Work Objectives

In order to bridge the gap between existing
problems, the main aim of this Thesis work is to
design a reconfigurable rectangular to polar
converter to optimize
(i) Area and
(ii) Speed,
by optimal resource consumption of the FPGA
target device for various precision values using
CORDIC Algorithm.

Design Methodology

Proposed Model Development

A finite precision model for implementing the Rectangular
to Polar Converter, based on the unfolded fully parallel
CORDIC architecturehas been developed using MATLAB /
Simulink and System Generator tools.

System Generator uses the Xilinx Blockset for Simulink and the
Xilinx Blockset is accessed via the Simulink Library browser which
can be launched from the standard MATLAB toolbar as shown on
the next slide.

Proposed Model Development

..Model Arrangement

Proposed Model Development

.. Proposed Model

Proposed Model Development

The proposed model as shown contains several System
Generator sub-system blocks.
designed using Xilinx Blockset.
and a separate Simulink arrangement for true rectangular to
polar conversion using only Simulink blocks.
Proper provisions for displaying the inputs as well as the
outputs.
The model has been developed by duplicating the equations
shown earlier for circular coordinate system (p = 1) and for
binary number systems ( = 2).
The precision of the input and output operands are upto 3
bytes with 8 number of binary point bits.

Proposed Model Development

The CORDIC algorithm converges for only angles between
-900 to +900, therefore, in order to support the full range of
input angles, the computation is decomposed into three
functions the coarse angle rotation, the fine angle rotation
and the angle correction.

performed by three main sub-systems shown as Quadrant Map, Fine

Angle Rotation and Quadrant Correct.

Proposed Model Development

.. Subsystems

Proposed Model Development

.. Blocks used from Xilinx and Simulink Blockset

Proposed Model Development

.. Special Purpose Blocks

Results and Discussions

The proposed model for the rectangular to
polar converter has been simulated with a
combination of MATLAB and Simulink. The
waveforms for the rectangular inputs x and
y; and magnitude and atan2 outputs, as
generated at the output of the simulink model
on a scope are shown on the next slide.

Results and Discussions

Results and Discussions

..Error Variance Data Statistics

Results and Discussions

..Error Variance Data Statistics

Results and Discussions

..Simulation for 12-bit precision

Results and Discussions

..Area Utilization for 12-bit precision

Results and Discussions

..Simulation for 14-bit precision

Results and Discussions

..Area Utilization for 14-bit precision

Results and Discussions

..Simulation for 16-bit precision

Results and Discussions

..Area Utilization for 16-bit precision

Results and Discussions

..Simulation for 18-bit precision

Results and Discussions

..Area Utilization for 18-bit precision

Results and Discussions

..Simulation for 20-bit precision

Results and Discussions

..Area Utilization for 20-bit precision

Results and Discussions

..Simulation for 22-bit precision

Results and Discussions

..Area Utilization for 22-bit precision

Results and Discussions

..Minimum Period and Maximum Frequency for

different wordlengths

Results and Discussions

.. Performance of the Proposed Architecture Based on

Fully Parallel CORDIC

Results and Discussions

.. Performance of the Architecture Based on LUT-based

Approach [51]

Results and Discussions

.. Comparison with other implementation strategies [51]

Results and Discussions

.. Discussions

The proposed architecture provides 15-30 % savings in the FPGA slices

when compared with the LUT-based method. The highest saving of 69.9
% is done with the 22-bit precision case.
The 4-input LUTs also provide area savings from 18-40 % for the
proposed fully parallel CORDIC architecture.
Though the number of flip-flops is increased in the proposed design but
the proposed design is not using any BRAM or multiplier, whereas the
efficiency of the existing architecture has mostly been degraded due to use
of BRAMs and multipliers in the LUT-based approach [51].
Furthermore, the proposed architecture increases the maximum clock
frequency, which is 3.56 times for the 22-bit precision model and 3.01
times for the 12-bit precision model.

Conclusion
The thesis has presented an architecture for rectangular-topolar conversion using an iterative linear convergence
algorithm CORDIC to increase the performance and reduce
the hardware size.
The
architecture
has
been
modelled
using
MATLAB/Simulink and System Generator software,
synthesized with ISE 10.1 software and implemented in a
VirtexII XC2V3000-4FG676 Xilinx FPGA device.
The hardware implementation of RPC using CORDIC on
FPGA is done as the FPGAs can give enhanced speed at low
cost with a lot of flexibility.

Conclusion
Moreover, the CORDIC algorithm provides hardware
efficient solution since the multipliers are replaced by adders
and shifters, which in turn reduce the gate count,
computational complexity, hardware cost and thereby
improves speed.
The alternate LUT-based technique requires huge memory
and is not worthwhile to be used in this era of
nanotechnology.
The proposed design in this Thesis work increases the
maximum frequency, reduces the number of FPGA slices
and is not utilizing multipliers and BRAMs with respect to
the existing LUT-based architecture.

Conclusion
As a result, the proposed architecture is most suitable for
high speed wireless communications and provides an
alternative for multiband and multimode operations that can
support various modulation formats such as EDGE, GSM,
CDMA, TDMA, and WCDMA and can overcome from the
problems associated with I/Q based transmitter design too.
Also as todays communication applications requiring
increasing word lengths and accuracy, the value of the
proposed architecture may grow increasingly evident in
comparison to other algorithms.
In addition, FPGA implementation has been providing a
feature of on-field reconfigurability.

Future Scope
A hybrid transmitter structure should be designed.
The model can be optimized for more number of
binary point bits in future for providing more
accuracy.
Further research can be done to reduce the power
consumption, while maintaining area and speed
efficiencies.
The future step can be to apply the proposed design
tactics to the development and manufacturing of a
prototype IC.

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Easy to see
Rectangular versus Polar Representations