Logic Families and Characteristics

Introduction
Gate Characteristics
Logic Families
Logic Family Characteristics
A Comparison of Logic Families
Complementary Metal Oxide Semiconductor
Transistor-Transistor Logic

Introduction
Earlier we looked at a range of digital
applications based on logic gates at
that time we treated the gates as
black boxes
We will now consider the construction
of such gates, and their
characteristics

Gate Characteristics
The inverter or NOT gate
consider the characteristics of a simple
inverting amplifier as shown below
we normally use only the linear region

Gate Characteristics
We can use an inverting amplifier as
a logical inverter but using only the
non-linear region

Gate Characteristics
We can use an inverting amplifier as
a logical inverter but using only the
non-linear region

Gate Characteristics
Choose input values to ensure that
always are outside of the linear region
as in (a)
Unlike linear amplifiers, use circuits with
a rapid transition between the nonlinear regions as in (b)

Gate Characteristics
Logic levels
The voltage ranges representing 0 and 1
represent the logic levels of the circuit
Often logic 0 is represented by a voltage close
to 0 V but the allowable voltage range varies
considerably
The voltage used to represent logic 1 also
varies greatly. In some circuits it might be 2-4
V, while in others it might be 12-15 V
In order for one gate to work with another the
logic levels must be compatible

Gate Characteristics
Noise immunity
Noise is present in all real systems
To cope with noise, the voltage ranges defining
the logic levels are more tightly constrained at
the output of a gate than at the input
Thus small amounts of noise will not affect the
circuit
The maximum noise voltage that can be
tolerated by a circuit is termed its noise
immunity, VNI

Gate Characteristics
Transistors as switches
Both FETs and bipolar transistors make
good switches
Both forms of device take a bit of time
to switch and this produces a slight
delay in the operation of the gate
This is termed the propagation delay
of the circuit

FET -Switch
The FET as a logical switch

FET-Switch characteristics
Rise and fall times
Because the waveforms are not
perfectly square there is a way of
measuring switching times
Measure the rise time, tr and fall time,
tf as shown below:

Bipolar Transistor logical

switch
The bipolar transistor as a
logical switch

Bipolar Transistor logical

switch
When the input voltage to a bipolar transistor is
high the transistor turns ON and the output voltage
is driven down to its saturation voltage which is
about 0.1 V
However, saturation of the transistor results in the
storage of excess charge in the base region
This increases the time taken to turn OFF the
device an effect known as storage time
This makes the device faster to turn ON than OFF
Some switching circuits increase speed by
preventing the transistors from entering
saturation

Propagation Delay time

Timing considerations
All gates have a certain propagation
delay time, tPD
This is the average of the two switching
times
t PD 21 (tPHL t PLH )

Logic Families
Different devices use different voltages ranges for
their logic levels
They also differ in other characteristics
In order to assure correct operation when gates are
interconnected they are normally produced in
families
The most widely used families are:
Complementary Metal Oxide Semiconductor
(CMOS)
Transistor-Transistor Logic (TTL)
Emitter-Coupled Logic (ECL)

Logic Family Characteristics

Complementary metal oxide semiconductor
(CMOS)
Most widely used family for large-scale devices
combines high speed with low power consumption
usually operates from a single supply of 5 15 V
excellent noise immunity of about 30% of supply voltage
Can be connected to a large number of gates (about 50)
Many forms some with tPD down to 1 ns
Power consumption depends on speed (perhaps 1 mW)

Logic Family Characteristics

Transistor-transistor logic (TTL)
Based on bipolar transistors
One of the most widely used families for small- and
medium-scale devices rarely used for VLSI
Typically operated from 5V supply
Typical noise immunity about 1 1.6 V
Many forms, some optimised for speed, power, etc.
High speed versions comparable to CMOS (~ 1.5
ns)
Low-power versions down to about 1 mW/gate

Logic Family Characteristics

Emitter-coupled logic (ECL)
Based on bipolar transistors, but removes
problems of storage time by preventing the
transistors from saturating
Very fast operation - propagation delays of 1ns
or less
High power consumption, perhaps 60 mW/gate
Low noise immunity of about 0.2-0.25 V
Used in some high speed specialist
applications, but now largely replaced by high
speed CMOS

A Comparison of Logic
Families
Parameter

CMOS

TTL

ECL

Basic gate

NAND/NOR

NAND

OR/NOR

>50

10

25

1 @ 1 MHz

1 - 22

4 - 55

Excellent

Very good

Good

1 - 200

1.5 33

1-4

Fan-out
Power per gate (mW)
Noise immunity
tPD (ns)

Complementary Metal Oxide

Semiconductor
A CMOS inverter

CMOS Circuits CMOS

Inverter

Complementary Metal Oxide

Semiconductor
CMOS gates

CMOS Characteristics
CMOS logic levels and noise
immunity

Transistor-Transistor Logic
Discrete TTL inverter and NAND
gate circuits

TTL Circuits
TTL Inverter

Transistor-Transistor Logic
A basic integrated circuit TTL
NAND gate

Transistor-Transistor Logic
A standard TTL NAND gate

TTL Circuits

TTL NAND gate

Transistor-Transistor Logic open

Collector
A TTL NAND gate with open
collector output

TTL Circuits

Open-collector TTL gates

Key Points
Physical gates are not ideal components
Logic gates are manufactured in a range of logic
families
The ability of a gate to ignore noise is its noise
immunity
Both MOSFETs and bipolar transistors are used in
gates
All logic gates exhibit a propagation delay when
responding to changes in their inputs
The most widely used logic families are CMOS and
TTL
CMOS is available in a range of forms offering high
speed or very low power consumption
TTL logic is also produced in many versions, each

Basic Operational Characteristics and Parameters

Logic levels

CMOS Circuits CMOS

Tristate CMOS gates

TTL Circuits

Schottky TTL NAND gate

Bus - Essential Part of Any

Computer
CPU

Primary
Memory

Secondary
Memory

I/O

Data
Address
Control

35

Tri-state Logic Outputs

Since we can have multiple masters on
a bus, we need Tri-state logic for
attachment to a bus so that each
device can choose to drive or not drive
the bus depending on whether it is the
bus master for a given bus cycle
Tri-state logic prevents a bus conflict
where one device is driving a signal to
1 and another device is driving it to 0
at the same time - generates high
current through wires (and smoke?)
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Tri-State Logic
The problem with connecting multiple
normal outputs together on a bus is that
each has to be in one logic state (0) or the
other (1) - driving voltage on each bus
signal high or low
This represents a conflict over the state of
the signal
Logically
Electrically
Truth Table
We resolve this conflict with tri-state logic
A

enable

+5v

output
0v

enable
0
0
1
1

A
0
1
0
1

Output
(Z)
(Z)
1
0

37

Tri-State Logic and Buses

The logical element has output enable pin to go
from a floating output to drive the output from the
circuit
Inverters and buffers are used as bus drivers or
buffers
Two such drivers or buffers in opposite directions are
used to make the connection bi-directional
The gates also provide more drive onto the bus so that
the bus signals are stronger and the bus can be longer
enablein

Bus

Device
enableout

38

Bus Master Slave

Relationships
During any specific bus cycle, only one device
attached to the bus is allowed to drive it
Driving the bus means that a device is forcing
each signal on the bus to a high or low state
For the data bus, the processor, a memory chip,
or an I/O device may be driving the data bus
during a specific read or write bus cycle
Specific signals on the address and control bus
select a device to be the master on the data
bus

39

Bus Arbitration
Bus arbitration is used to hand off a
bus between one of several potential
bus masters using signals that are a
part of the bus itself
A bus arbitration protocol
implements some form of bus
request and bus grant handshake to
determine which device will be the
master on the bus for the next bus
cycle

40

Bus Master Slave

Relationships
Other devices that potentially can be
the master on the address and
control bus are:
Direct Memory Access (DMA) Controller
DRAM controller to refresh the stored
bits
Other processors in multiprocessor
architectures

Well only discuss the first application

above, but not at the level of

41

Direct Memory Access

You thought that handling an I/O device
under interrupt control was pretty good
right?
Wrong!
The overhead to process an interrupt for
each byte of data is still relatively costly in
terms of processor time

Process interrupt and stack context of processor

Fetch and execute instructions of ISR
Move data from I/O device or memory to
processor register
Move data from processor register to memory or
I/O device
Restore context of processor and resume
42
background code

Direct Memory Access

We add a DMA Controller (DMAC) to our
system, e.g. Intel 8237A DMA controller
chip
The DMAC has the capability of becoming
the bus master on the address and control
bus for one or more channels
transferring data between an I/O device
and memory, e.g. 8237A supports 4
channels
We connect DMA Request and DMA
Acknowledge signals between the I/O
device and the DMAC
Software in the CPU sets up the DMAC to
43
transfer an entire sequence of bytes

DMAC Operation
When requested, the DMAC arbitrates with
the CPU to be the master on the address
and control busses
It executes a bus cycle to transfer a byte
of data from memory (or I/O device) to I/O
device (or memory)
While DMA controller is bus master, the
CPU can not access memory or I/O devices
This is called Cycle Stealing (the DMA
controller steals bus cycles from the
processor)
44

DMAC Bus Arbitration

I/O Device

DMAC

DMA Request

Memory

Processor

Hold Request Asserted

Time

Hold Acknowledge asserted

DMA Acknowledge
Data Transfer to/from Memory via Busses)Cycle Stealing
Time Interval
Data Transfer to/from Memory via Busses)
Hold Request De-asserted
Hold Acknowledge de-asserted

45

Tri-State Bus Summary

All devices have tri-state logic
connections to the data bus may be
driving or receiving
Memory and I/O devices dont need
tri-state logic on address/control bus
(never drive them)
Because the processor may need to
yield the control/address busses, it
must have tri-state logic for driving
those bus signals
DMAC controller must have tri-state

46

Hi-Impedance Outputs

Logic gates introduced thus far

have 1 and 0 output values,

cannot have their outputs connected together, and
transmit signals on connections in only one direction.

Three-state logic adds a third logic value, HiImpedance (Hi-Z), giving three states: 0, 1, and
Hi-Z on the outputs.
The presence of a Hi-Z state makes a gate output
as described above behave quite differently:
1 and 0 become 1, 0, and Hi-Z
cannot becomes can, and
only one becomes two

Hi-Impedance Outputs
(continued)

What is a Hi-Z value?

The Hi-Z value behaves as an open circuit
This means that, looking back into the circuit,
the output appears to be disconnected.
It is as if a switch between the internal circuitry
and the output has been opened.

Hi-Z may appear on the output of any gate,

but we restrict gates to:
a 3-state buffer,

The 3-State Buffer

For the symbol and truth
table, IN is the data input,
and EN, the control input.
For EN = 0, regardless of
the value on IN (denoted
by X), the output value is
Hi-Z.
For EN = 1, the output
value follows the input
value.
Variations:
Data input, IN, can be
inverted
Control input, EN, can be
inverted
by addition of bubbles to

Symb
ol

IN

OUT

EN

Truth
Table
EN IN
0
1
1

X
0
1

OUT
Hi-Z
0
1