Power Aware BIST - I - 16.1.2012

Power Aware BIST for Digital ICs
Prepared by: Project Guide:

Anu Prema Rajendran Prof S.R. Pandey
M.Tech. (VLSI Design)
3rd Sem 2012,R.C.O.E.M. Nagpur
Department of Electronics
Engineering
Outline
Introduction
Project Motivation
Project Objective
Problem Statement
Literature Survey
Proposed Work
Plan of Research Work
References
Engineering
Introduction:
Ever growing scale, complexity & shrinking
process feature sizes make the design of VLSI
circuits highly prone to design errors & their
fabrication to manufacturing defects.
VLSI Testing consists of:
1) Applying test stimuli to the CUT

2) Measuring actual circuit responses.
3) Comparing them with expected circuit
responses.
)2 basic goals in VLSI Testing.
1) High test quality

2) Low test costs
Engineering
Introduction:
The power consumption of the chip during
manufacturing test can be significantly higher than
the power consumption of the chip in its system.
Main cause: extremely random test pattern
generation.
The correlation between consecutive vectors during
testing, is increased to creating low transition
density in the pattern sets and thus control the
power dissipation.
This in turn increases the test application time.
This research aims to provide a way to deal with
the problems of power constraint in BIST circuits
and test application time.
Engineering
Project Motivation
The increase in the power consumption of

the IC in the test mode is well known in the
industry to cause sudden unrepairable
device failures resulting in significant
manufacturing fall-out directly impacting the
cost of the IC.
Today a combination of external Automated

Test Equipment (ATE) and internal BIST
(Built-In-Self-Test) techniques are used to
ensure the highest possible fault coverage of
the device at the lowest possible cost.
Engineering
Project Objective
Test Pattern generation has long been

carried out by using conventional Linear
Feedback Shift Registers.
The power consumed by the CUT is a

measure of the switching activity of the logic
inside the chip which depends largely on the
randomness of the applied input stimulus.
Reduced correlation result in much higher

power consumption by the device.
Engineering
Problem Statement
To provide a way to deal with the
problems of power constraint in
Testing of Digital ICs circuits and test
application time.
Engineering
Literature Survey
Wang proposed a Research and Design of Low

Power Consumption Testing Generator for ICs.
In this paper, Sources of power consumption for
CMOS logical circuits are analyzed and several BIST
technologies of low power consumption are
summarized.
In order to reduce the switching activity rate of
internal nodes in CUT and raise the correlation
between testing vector, a test theory is introduced.
It can reduce the switching activity rate of nodes in
the circuit-under-test to realize low power
consumption during testing without lossing fault
coverage.
Engineering
Literature Survey Cont.
Girardproposed a technique to minimize the
energy required to test combinational circuits
with BIST without altering fault coverage .
They have analyzed the impact of the

polynomial and seed selection of the LFSR
used as TPG on the energy consumed by the
circuit and found that appropriate selection of
the seed of the LFSR can contribute to energy
reduction whereas the polynomial selection
does not affect the power consumption.
Engineering
Proposed Work
Basic BIST circuitry
Engineering
BIST
BIST is a DFT technique in which additional
hardware is added to the circuit to be tested
so that it can test itself.
LFSR generates pseudorandom patterns
required for test.
Test-Per-Clock BIST systems: new set of
faults is tested in every clock cycle.
Test-Per-Scan BIST systems: each test
comprises scan-in of one input vector, one
clock to conduct the test and scan-out of
output responses. Large test time and
simulation time required.
Engineering
Plan of Research Work
Engineering
References
X.Wen VLSI Testing and Test Power, Kyushu
institute of Technology Iizuka.
A.Farlooqi Low Power Test Pattern Generation
For System On Chip Devices, May 2006.
X. Wen Power Aware Testing And Test
Stratergies For Low Power Devices.
F.Rashid Controlled Transition Density Based
Power Constrained Scan-BIST With Reduced
TimeMay 2012.
P. Girard, Survey of Low-Power Testing of VLSI
Circuits, IEEE Design & Test of Computers,
vol. 19, no. 3, pp. 8090, May-June 2002.
Engineering
Suggestions.
Engineering
Thank you
Engineering

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Power Aware BIST for Digital ICs

Prepared by: Project Guide:

1) Applying test stimuli to the CUT

1) High test quality

The increase in the power consumption of

Today a combination of external Automated

Test Pattern generation has long been

The power consumed by the CUT is a

Reduced correlation result in much higher

Wang proposed a Research and Design of Low

They have analyzed the impact of the

Basic BIST circuitry

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