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DOI: 10.4172/2332-0796.1000148

Electrical & Electronic Systems

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ISSN: 2332-0796

Research Article
Research Article OpenAccess
Open Access

Analysis of Power Reduction Techniques used in Testing of VLSI Circuits

Shaktisinh Karnubha Jadeja*, Rajendra Patel and Jayesh Popat
Marwadi Education Foundation, Rajkot, Gujarat, India

Abstract
One of the most important parameter over the past decade in VLSI design is the Power dissipation during
manufacturing test, as the circuit consume much more power during test than functional mode of operation. This paper
presents analysis of low power testing techniques by which Power optimized test patterns are obtained. The compaction
technique has been validated using benchmark examples, and it has been shown that average 33% of test patterns
have been reduced by which power is minimized. Evaluation of various techniques under consideration in this paper is
carried out by open source tool ATALANTA for test pattern generation and MATLAB for optimization.

Keywords: Test pattern; BIST (Built in Self-Test); Test data reordering; the information about number of primary inputs, number of primary
Test data compression outputs, number of gates, logic level of circuit, fault coverage and
numbers of test patterns.
Introduction
Generated test pattern undergoes two different techniques which is
Testing is a process which ensures that the response of each test pattern compaction technique and test pattern reordering technique
fabricated circuit is acceptable. Production of authentic VLSI circuits to obtain power optimized test patterns. Test pattern compaction
depends strongly on testing which eliminates various faults caused by technique removes the test cubes which are identical and reduces the
the fabrication processes. Switching activity increases during testing test pattern volume whereas test pattern reordering technique reduces
of different circuits compared to the normal operation of the circuit the switching between two patterns therefore the number of transition
which raises the power dissipation and hence may lead to lower circuit reduces. At the end compression bits are measured in percentage in the
manufacturing yield and reliability [1]. Different prominent approaches section IV.
for low power VLSI testing which are well proven and widely used
are discussed in. Combining compaction and test vector ordering Test Pattern Compaction Technique
technique reduces power dissipation during testing of combinational The aim of test compaction is to cut down the number of final
and sequential VLSI circuits. Experimental results, using compact and test vectors. Test power reduction can also be achieved through test
non-compact test sets, have shown that compact test sets have similar pattern compaction. Compaction is the work of combining multiple
power dissipation during testing different circuits with reduction in test cubes into one if they are compatible. Two test cubes, c1 and c2,
testing time and computational time when compared to non-compact are said to be compatible if two corresponding bits in c1 and c2 do
test sets. not have opposite logic values [4]. Conventionally, compaction is
Test Pattern Generation
Test pattern generation is an important part of the VLSI testing
flow that offers many possibilities that can be explored for reducing
test power dissipation. The most significant advantage of reducing test
power through low power test pattern generation is that this approach
causes neither circuit overhead nor performance degradation. ATALANTA
However, low-power test pattern generation is a technical field, in
which many important factors in addition to the effect of test power
reduction has to be considered. Such factors include test vector count
inflation, potential fault coverage loss, increased test pattern generation
time, compatibility with compressed scan testing and test generation
flow modification as discussed in. Low power Automatic Test Pattern
Figure 1: Atalanta Results.
Generation (ATPG) is an advanced class of ATPG that targets.
Test power reduction in addition to fault sensing during test cube
generation [2]. General test generation targets combinational and
sequential circuits. The goal of general low-power test generation is *Corresponding author: Shaktisinh Karnubha Jadeja, Marwadi Education
Foundation, Electronics and Communication, 9 Neels Bungalow, Near Saurastra
to create a sequence of test vectors that cause a minimal number of University, Rajkot, Gujarat, India, Tel: + 91-8460235938; E-mail: jadeja87@gmail.com
transitions at inputs between any two consecutive cycles.
Received May 13, 2015; Accepted June 09, 2015; Published June 25, 2015
The Table 1 represents various benchmark circuits, taken from Citation: Jadeja SK, Patel R, Popat J (2015) Analysis of Power Reduction
ISCAS’85 benchmark suite, used in this research work (Figure 1). Techniques used in Testing of VLSI Circuits. J Electr Electron Syst 4: 148.
Atalanta [3] is an open source tool used for Automatic Test pattern doi:10.4172/2332-0796.1000148
generation and Fault simulator. Test pattern generation results include Copyright: © 2015 Jadeja SK, et al. This is an open-access article distributed under
circuit structure, ATPG parameters, test pattern and fault simulation. the terms of the Creative Commons Attribution License, which permits unrestricted
use, distribution, and reproduction in any medium, provided the original author and
Table 1 shows result of test pattern generation which includes source are credited.

J Electr Electron Syst

ISSN: 2332-0796 JEES an open access journal Volume 4 • Issue 2 • 1000148
Citation: Jadeja SK, Patel R, Popat J (2015) Analysis of Power Reduction Techniques used in Testing of VLSI Circuits. J Electr Electron Syst 4: 148.
doi:10.4172/2332-0796.1000148

Page 2 of 3

Benchmark Number of Primary Number of Primary Number of Logic Level Fault Coverage Number of
Circuit Inputs Output Gates of Circuit In % Test Patterns
C17 5 2 6 3 100 7
C432 36 7 160 17 99.237 69
C499 41 32 201 11 98.945 85
C880 60 26 383 24 100 98
C1355 41 32 546 24 99.492 110

Table 1: Test Pattern Generation For Different Bench Mark Circuits.

Benchmark Number of Test Pattern Reduction in Test

circuit Before After Patterns (%) Test Pattern
Compaction Compaction
C17 7 5 28.57
C432 69 46 33.33 Measures
Length of Test
C499 85 53 37.65 pattern
C880 98 57 41.83
C1355 110 84 23.64
Measures
Table 2: Test pattern compaction using atalanta. Hamming
Distances

Arrange the
test
patterns
Test Pattern
Compaction using
ATALANTA Reordered test patterns

Figure 3: Test pattern reordering.

Compacted test patterns

01110 01110
3 2
Test Pattern 10111 11010
Reordering using 3 3
MATLAB 10000 10111
2 2
11010 00101
5 2 2
Figure 2: Optimized test pattern flow.
00101 10111

(a) (b)
conducted to reduce the final test vector count, it can also reduce test
Figure 4: Test patterns (A) Original Sequence (b) Reordered Sequence.
power if power is considered when compatible test cubes are merged.
Compaction technique selects a target fault in such a manner that the
risk of violating capture power limits is minimized [5]. hamming includes following steps which are demonstrated with
Compaction of test patterns is done on different benchmark example of C17 benchmark circuit (Figure 3).
circuits using ATALANTA tool. Table 2 shows number of test patterns Steps of Reordering [5,6] are given in Figure 4.
before and after compaction for each benchmark circuit.
The example in Figure 4 shows the reduction in transition with the
Using test pattern compaction the average reduction of 33% in test help of reordering. Test pattern of C17 benchmark circuit are reorder
patterns is observed. Test pattern reordering is done on compacted test to minimize switching between test patterns.
vectors for reducing switching activity (Figure 2).
As power is directly proportional to the switching activity as show
Test Pattern Reordering Technique in Equation, Power can be reduce by reducing switching (transition)
Test pattern reordering technique minimizes the number of between patterns.
transition between all the patterns. Reordering can be done using Pα CV 2 (1)
different algorithms like Shortest Path Algorithm, Traveling Salesman
Problem (TSP), Simulated Annealing (SA), Hamming Distance, Where
Genetic Algorithm (GA) [6], and Ant Colony Optimization [3]. ∝ is Switching activity
In this paper Hamming distance based ordering is done for C is capacitance
minimization of transition between test patterns. Reordering using

J Electr Electron Syst

ISSN: 2332-0796 JEES an open access journal Volume 4 • Issue 2 • 1000148
Citation: Jadeja SK, Patel R, Popat J (2015) Analysis of Power Reduction Techniques used in Testing of VLSI Circuits. J Electr Electron Syst 4: 148.
doi:10.4172/2332-0796.1000148

Page 3 of 3

Benchmark Number of Transition Reduction (Table 4). Test stimulus compression should be an information lossless
circuit test pattern in procedure with respect to the specified (care) bits in order to preserve
Transition
Before After ordering (%) the fault coverage of the original test cubes. After decompression, the
ordering resulting test patterns shifted into the scan chains should match the
C17 5 13 9 30.77 original test cubes in all the specified (care) bits.
C432 46 2961 1832 38.13
C499 53 1052 754 28.50 Conclusion
C880 57 7638 5498 28.02
In this paper we have presented different power reduction
C1355 84 16535 12457 24.66
techniques used during testing of VLSI circuits. This techniques is
Table 3: Results for reordering technique. applied on test pattern to minimize test data volume and switching
activity. Combining the different technique like compaction and test
Benchmark circuit Compressed Bits vector ordering technique, reduction in Power dissipation during
C17 10 testing combinational and sequential circuits. The proposed techniques
C432 828 better compression with no penalty in area and time. This techniques
C499 1312 can be easily adopted for power reduction.
C880 2460
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J Electr Electron Syst

ISSN: 2332-0796 JEES an open access journal Volume 4 • Issue 2 • 1000148