Scribd
Upload
74 views14 pages

A Novel Approach For Constructing Reversible Fault Tolerant N-Bit Binary Comparator

This document proposes a novel approach for constructing reversible fault tolerant n-bit binary comparator circuits. It discusses how conventional comparator designs using logic gates like XOR and NOR are irreversible and dissipate energy as heat. Reversible logic gates allow low power circuit design by reducing heat dissipation to zero if the circuit is designed reversibly. The document outlines conditions for reversible gate design, including one-to-one input-output correspondence and balance/dual conditions. It then proposes a design for a reversible n-bit comparator using fault tolerant reversible gates to detect faults while preserving parity between inputs and outputs.

Uploaded by

Ajay Kumar Mattupalli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
74 views14 pages

A Novel Approach For Constructing Reversible Fault Tolerant N-Bit Binary Comparator

This document proposes a novel approach for constructing reversible fault tolerant n-bit binary comparator circuits. It discusses how conventional comparator designs using logic gates like XOR and NOR are irreversible and dissipate energy as heat. Reversible logic gates allow low power circuit design by reducing heat dissipation to zero if the circuit is designed reversibly. The document outlines conditions for reversible gate design, including one-to-one input-output correspondence and balance/dual conditions. It then proposes a design for a reversible n-bit comparator using fault tolerant reversible gates to detect faults while preserving parity between inputs and outputs.

Uploaded by

Ajay Kumar Mattupalli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 14

A Novel Approach for Constructing

Reversible Fault
Tolerant n-Bit Binary Comparator

Under the esteemed guidance of


Smt V.SANTHI SRI.
presented by
M V Ajay kumar
INTRODUCTION

• Comparator circuits are one of the most


important and commonly used circuits for
computing systems like Detectors, ADC/DAC,
ALU, Device Interfaces, in Communications
Systems etc. Conventional comparator circuit’s
designs are based on logic gates like XOR,
NAND NOR etc. During such operation some
bits are erased and thus dissipated energy in
the form of heat. Such operations are called as
irreversible logic operations.
Irreversible logic operations

• Conventional comparator circuit’s designs are


based on logic gates like XOR, NA ND NOR etc.
During such operation some bits are erased
and thus dissipated energy in the form of
heat. Such operations are called as irreversible
logic operations.
Reversible Logic Gates

• Thus stringent requirement for low power


circuit design has been a big issue in most
comparator circuits. According to C.H. Bennet,
power consumption and heat dissipation can
be ideally reduced to zero if the circuit is
designed using Reversible Logic Gates.
REVERSIBLE LOGIC GATE ADVANTAGE
REVERSIBILITY CONDITIONS
A reversible gate design should satisfy the following three
conditions.
• Condition 1
One to One correspondence between input and outputs also
known as “Bijective Conditions”.
• Condition 2
Each output function must be equal to 1 for its half of the
inputs, known as “Balance Conditions”.
• Condition 3
By inversing output, we must be able to reproduce mapped
input called as “Dual” or “Inverse Conditions”.
REVERSIBLE LOGIC CIRCUIT
OPTIMIZATION PARAMETERS
Fault Tolerant Gate

• It is used to detect error of a reversible gate which


constantly preserves same parity values between input
and output vectors. I1^ I2^I3…^In= O1^O2^O3…^On It
is the parity preserving property that allows detecting a
faulty signal from the circuit’s output. When a reversible
circuit is implemented using only fault tolerant reversible
gates, the entire circuit itself preserves parity and thus, it
should be able to detect fault.
Proposed Design of Fault Tolerant
Reversible n-Bit Comparator.
• A>B---- 53 57
27 52

10
10
G
g1
1

e0 go
• A<B---- 72 27
93 29

10

10
L
l1
1

lo
e0
A=B---- 55
55

10
e1

eo
THANK YOU...

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy