Memories and PLDs

 A memory unit is a device to which binary information is transferred for storage
and from which information is retrieved when needed for processing.
 Units of Binary Data
 Bit
 Byte
 Nibble
 Word
 Each storage element in memory can retain either a 1 or 0 and called a cell
 Memories are made up of arrays
• Static RAM (SRAM) consists essentially of internal Latches that store
the binary information.
• Dynamic RAM (DRAM) stores the binary information in the form of

electric charges on capacitors provided inside the chip by MOS
transistors (require refreshing).
Its Non-Volatile Memory (Store data even without power)
.
 Programmable Logic Devices: These are special types of IC’s used by the user
and are programmed before use. Different types of logic functions can be
implemented using a single programmed IC chip of PLD’s.
 ASICs all have fixed functions, determined by the logic circuit for each component.
 Programmable logic devices (PLDs), on the other hand, can be programmed after
manufacture to have different functions
 Part 1 - Programmable Implementation Technologies
 Why Programmable Logic?
 Programmable Read-Only Memories (PROMs)
 Programmable Logic Arrays (PLAs)
 Programmable Array Logic (PALs)
 Facts:
 It is most economical to produce an IC in large volumes
 Many designs required only small volumes of ICs
 Need an IC that can be:
 Produced in large volumes
 Handle many designs required in small volumes
 A programmable logic part can be:
 made in large volumes
 programmed to implement large numbers of different low-volume
designs
 Many programmable logic devices are field- programmable, i. e., can
be programmed outside of the manufacturing environment
 Most programmable logic devices are erasable and

reprogrammable.
 Allows “updating” a device or correction of errors
 Allows reuse the device for a different design - the ultimate in re-usability!
 Ideal for course laboratories
PROGRAMMABLE CONFIGURATIONS
 Programmable Read Only Memory (PROM) - a fixed array
of AND gates and a programmable array of OR gates
 Programmable Array Logic (PAL) - a programmable array
of AND gates feeding a fixed array of OR gates.
 Programmable Logic Array (PLA) - a programmable array
of AND gates feeding a programmable array of OR gates.
 Complex Programmable Logic Device (CPLD) /Field-
Programmable Gate Array (FPGA)
ROM, PAL AND PLA CONFIGURATIONS
Fixed Programmable Programmable

Inputs AND array OR array Outputs
(decoder) Connections
(a) Programmable read-only memory (PROM)
Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array
(b) Programmable array logic (PAL) device
Programmable Programmable Programmable Programmable

Inputs Outputs
Connections AND array Connections OR array
(c) Programmable logic array (PLA) device

.
READ ONLY MEMORY
 Read Only Memories (ROM) or Programmable Read Only
Memories (PROM) have:
 N input lines,
 M output lines, and
 2N decoded minterms.
 Fixed AND array with 2N outputs implementing all N-literal

minterms.
 Programmable OR Array with M outputs lines to form up to
M sum of minterm expressions.
READ ONLY MEMORY
 A program for a ROM or PROM is simply a multiple-output truth
table
 If a 1 entry, a connection is made to the corresponding minterm for the corresponding output
 If a 0, no connection is made
 Can be viewed as a memory with the inputs as addresses of

data (output values), hence ROM or PROM names!
 Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)
 The fixed "AND" array is a
“decoder” with 3 inputs and 8 D7
D6
X X X
outputs implementing min-terms. D5 X X

D4 X
 The programmable "OR“ A A2 D3
array uses a single line to B
D2
A1 D1
X
X X
represent all inputs to an C A0 D0 X
OR gate. An “X” in the
array corresponds to attaching the
min-term to the OR
F3 F2 F1 F0
 What are functions F3, F2 , F1 and F0 in terms of (A,B,C)?

 F3=ABC+AB’C+A’BC’
 F2=ABC+A’B’C’
 F1=A’B’C+AB’C’
 F0=ABC+AB’C+A’B’C
Chapter 6 - Part 4 26
 F1=A’BCD+A’B’CD’+ABCD+ABC’D+ABCD’
 F2=AB’C’D’+A’B’C’D’+ABCD+A’B’CD
 F3=ABCD+A’B’C’D’
 F4=ABCD’+A’B’CD’+AB’CD
Chapter 6 - Part 4 27
 Design a Half Adder using PROM
 Design a 3 Bit Binary to Gray code converter using PROM.
PAL (Programmable Array Logic)
PLA (Programmable Logic Array)
.
Programmable Array Logic
In PAL only AND gates array is programmable, whereas OR array is fixed
 The product term of a programmable array logic (PAL) can not be shared by
multiple OR gates.
 Besides, the number of inputs of the OR is fixed , e.g.
.
Programmable Logic Array
In PLA’s both AND gates and OR gates are programmable.

 A programmable logic array (PLA) with n inputs and m outputs is a device that can realize m
functions of n variables by means of sum-of-products.
 A PLA consists of an AND array with n input lines and a OR array with m output lines
 Several Logic functions can be realized on a single chip.
 Highly Economical, when no. of functions to be realized is high.
 Easy to design any complex logic circuit or boolean function.
Problem 1: Implement following functions using PAL:
 Y0=A+BD’+CD’
 Y1=ABC’D’+A’B’CD
 Y2=AB’C
 Y3=AB+C’D’
 Problem 2: Implement the boolean function using PAL;
Y1 = ∑ m (1,3,5,7)
Y2 = ∑ m (2,4)
 Problem 3: Implement following using PLA:

F = A’BC+ABC’+A’B’C’+AC’

Memories and PLDs

Uploaded by

Copyright:

Available Formats

Memories and PLDs

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Memories and PLDs

Uploaded by

Copyright:

Available Formats

 A memory unit is a device to which binary information is transferred for storage

and from which information is retrieved when needed for processing.

 Units of Binary Data

• Dynamic RAM (DRAM) stores the binary information in the form of

 Most programmable logic devices are erasable and

Fixed Programmable Programmable

(a) Programmable read-only memory (PROM)

Programmable Programmable Fixed

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

(c) Programmable logic array (PLA) device

 Fixed AND array with 2N outputs implementing all N-literal

 Can be viewed as a memory with the inputs as addresses of

outputs implementing min-terms. D5 X X

 What are functions F3, F2 , F1 and F0 in terms of (A,B,C)?

Programmable Logic Array

In PLA’s both AND gates and OR gates are programmable.

 Problem 3: Implement following using PLA:

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.