Programmable Logic Devices

Why Programmable Logic?

Facts:
It is most economical to produce an IC in large volumes
Many designs required only small volumes of ICs
Need an IC that can be:
Produced in large volumes
Handle many designs required in small volumes
A programmable logic part can be:
made in large volumes
programmed to implement large numbers of different low-volume designs

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 Programmable Logic - Additional
Advantages
- Many programmable logic devices are field- programmable, i. e., can
be programmed outside of the manufacturing environment
Most programmable logic devices are erasable and reprogrammable.

Allows “updating” a device or correction of errors

Allows reuse the device for a different design - the ultimate in reusability!

- Programmable logic devices can be used to prototype design that will

be implemented for sale in regular ICs.

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 Technology Characteristics
Permanent - Cannot be erased and reprogrammed
- Mask programming - Fuse - Antifuse
Reprogrammable
Volatile - Programming lost if chip power lost
Single-bit storage element
Non-Volatile
- Erasable - Electrically erasable - Flash

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 PLD Structure

Inputs

Dense array of Dense array of

AND gates Product OR gates
terms

Outputs

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 PROM, PAL and PLA Configurations
Fixed
Programmable
Programmable
Inputs AND array
Connections OR array Outputs
(decoder)

(a) Programmable read-only memory (PROM)

Programmable
Programmable Fixed
Inputs Connections AND array OR array Outputs

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

Inputs AND array Connections OR array Outputs
Connections
(c) Programmable logic array (PLA) device
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Programmable Read-Only Memory

PROM
4 x 2 PROM with AND OR gates

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4 x 2 PROM with AND-OR-Inverter gates

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Combination logic Implementation

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 ROM
• ROM D7 X X X
D6
➢ A decoder D5 X X
➢ A set of programmable D4 X

OR’s A A2
D3
X
D2
B A1 D1 X X
A0 D0 X
C

F3 F2 F1 F0

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 Example
Find a ROM-based circuit implementation for:
f(a,b,c) = a’b’ + abc
g(a,b,c) = a’b’c’ + ab + bc
h(a,b,c) = a’b’ + c

Solution:
Express f(), g(), and h() in m() format (use truth tables)
Program the ROM based on the 3 m()’s

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 Example
There are 3 inputs and 3 outputs, thus we need a 8x3
ROM block.
f = m(0, 1, 7)
g = m(0, 3, 6, 7)
a 0

h = m(0, 1, 3, 5, 7) 1
2
3-to-8 3
b decoder
4
5
6
7
c

f g h
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 ROM as a Memory
Read Only Memories (ROM) or Programmable Read Only Memories
(PROM) have:
N input lines,

M output lines, and

2N decoded minterms.

Can be viewed as a memory with the inputs as addresses of data

(output values),
hence ROM or PROM names!

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 Programmable Logic Array

 Pre-fabricated building block of many AND/OR gates (or

NOR, NAND) "Personalized" by making/ breaking
connections among the gates.

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Construction of PLA

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Logic function implementation using PLA

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 Constants
Sometimes a PLA output must
be programmed to be a
constant 1 or a constant 0.
− P1 is always 1 because
its product line is
connected to no inputs
and is therefore always
pulled HIGH;
− this constant-1 term
drives the O1 output.
No product term drives the O2
output, which is therefore
always 0.
Another method of obtaining a
constant-0 output is shown for
O3.
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 Example
Implement the following functions using PLA
A B C

F0 = A + B' C'
F1 = A C' + A B AB
F2 = B' C' + A B
B’C
F3 = B' C + A
AC’

B’C’

F0 F1 F2 F3

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Programmable Logic Array Example
A

C
X X 1 X X AB

X X 2 X BC X Fuse intact
Fuse blown
X X 3 X AC

X X 4 X AB
X 0
C C B B AA
X 1
F1

F2
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 PALs

• Programmable Array Logic

 a fixed OR array.

Inputs

Dense array of Dense array of

AND gates Product OR gates
terms

Outputs

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Logic function implementation using PAL
B

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PAL
inputs

1st output
section

2nd output Only functions with

section at most four
products can be
implemented
3rd output
section

4th output
section

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 PAL

x x x
x x
x
x
x x x
x x x
x x x
x x x
x x x
x x x
x x x
x

W = ABC + CD
X = ABC + ACD + ACD + BCD
Y = ACD + ACD + ABD

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 Programmable Array Logic Example AND gates inputs
0 1 2 3 4 5 6 7 8 9
X
Product 1
term
4-input, 3-output PAL with fixed, 3- 2
X X
F1

input OR terms 3

What are the equations for F1 I 15 A

X X X
4
through F4? X X
5 F2
F1 = X X
6
F2 = I2 5 B

F3 =
X X
7

F4 =
X X
8 F3
X
9
I3 5 C
X X
10
X X
11 F4
X
12

I4
0 1 2 3 4 5 6 7 8 9
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Implement using PAL

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 BCD to Gray Code Converter
A B C D W X Y Z A A
0 0 0 0 0 0 0 0 AB AB
0 0 0 1 0 0 0 1 CD 00 01 11 10 CD 00 01 11 10
0 0 1 0 0 0 1 1 00 0 0 X 1 00 0 1 X 0
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 1 1 1 0 01 0 1 X 1 01 0 1 X 0
0 1 1 0 1 0 1 0 D D
0 1 1 1 1 0 1 1 11 0 1 X X 11 0 0 X X
1 0 0 0 1 0 0 1 C C
1 0 0 1 1 0 0 0 10 0 1 X X 10 0 0 X X
1 0 1 0 X X X X
1 0 1 1 X X X X B B
1 1 0 0 X X X X
K-map for W K-map for X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X A A
AB AB
CD 00 01 11 10 CD 00 01 11 10

00 0 1 X 0 00 0 0 X 1

Minimized Functions: 01 0 1 X 0 01 1 0 X 0
D D
11 1 1 X X 11 0 1 X X
W=A+BD+BC C C
X = B C' 10 1 1 X X 10 1 0 X X
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D' B B
K-map for Y K-map for Z

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 A B C D

BD
4 product terms per each OR gate BC

BC’

Product terms cannot be shared !

B
PLA achieves higher C
flexibility at the cost of
lower speed!

BCD

AD’

BCD’

W X Y Z
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 Comparison between PROM, PLA and PAL
S.No. PROM PLA PAL
1 AND array is fixed and OR Both AND array and OR array are AND array is programmable and
array is programmable programmable OR array is fixed
2 Flexible to the designer More flexible to the designer Flexible to the designer
3 Cheap and Simple to use Costly and complex as compared to Cheaper and Simple
PRAOM and PAL.
4 All minterms are decoded. AND array can be programmed to get the AND array can be programmed
desired minterms. to get the desired minterms.
5 Only Boolean functions in Any Boolean function in the SOP form can Any Boolean function in the
sum of minterms forms can be implemented SOP form can be implemented
be implemented.
6 The number of The number of interconnections (fuses) is The number of interconnections
interconnections (fuses) is 2n 2n x k + k x m + m, where n is number of (fuses) is 2n x k, where n is
x m, where n is number of inputs, k is number of product terms and m number of inputs and k is
inputs and m is number of is number of outputs (less) number of product terms. (less)
outputs (more)

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