+

William Stallings
Computer Organization
and Architecture
10th Edition

Adapted from © 2016 Pearson Education,

Inc., Hoboken, NJ. All rights reserved.
+ Chapter 5
Bus Systems

Adapted from © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
 A communication pathway Signals transmitted by any one
connecting two or more devices device are available for reception
• Key characteristic is that it is a shared by all other devices attached to
transmission medium the bus
• If two devices transmit during the same
time period their signals will overlap
and become garbled

Typically consists of multiple

communication lines
• Each line is capable of transmitting
Computer systems contain a
number of different buses that Bus
signals representing binary 1 and provide pathways between
binary 0 components at various levels of
the computer system hierarchy
Interc
onnect
ion
System bus
• A bus that connects major computer
components (processor, memory, I/O)
The most common computer
interconnection structures are
based on the use of one or more
system buses

Adapted from © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
 Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be transferred at a

time

 The width of the data bus

is a key factor in
determining overall
system performance

Adapted from © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+ Address Bus Control Bus

 Used to designate the source or

 Used to control the access and the
destination of the data on the data bus
use of the data and address lines
 If the processor wishes to read a
word of data from memory it puts  Because the data and address lines
the address of the desired word on are shared by all components there
the address lines must be a means of controlling their
use
 Width determines the maximum
possible memory capacity of the  Control signals transmit both
system command and timing information
among system modules
 Also used to address I/O ports
 The higher order bits are used to  Timing signals indicate the validity
select a particular module on the of data and address information
bus and the lower order bits select
a memory location or I/O port  Command signals specify operations
within the module to be performed
Adapted from © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
 CPU Memory Memory I/O I/O

Control lines

Address lines Bus

Data lines

Figure 3.16 Bus Interconnection Scheme

Adapted from © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+ 7

Operation of the bus

 If one module wishes to send data to another

 Obtain the use of the bus, and
 Transfer data via the bus

 If the module wishes to request data from another module

 Obtain the use of the bus, and
 Transfer a request to the other module over the appropriate control
and address bus lines
 It must then wait for the second module to send the data
+ 8

Internal and External Buses

 Internal bus
 a bus located strictly within a CPU chip for communications among
the components in a CPU chip

 External bus
 outside a CPU chip for connecting the rest of the system
components to the CPU.
 External buses are supported by third-party hardware and software,
and are more likely to adhere to one of a number of industry
standards for buses
+ 9

Bus Hierarchy
 Most modern PCs have at least four buses.
 The Processor Bus (System Bus):
 This is the highest-level bus that the chipset uses to send information to and
from the processor.

 The Cache Bus (Backside Bus):

 Higher-level architectures, employ a dedicated bus for accessing the system
cache.
 Conventional processors using fifth-generation motherboards and chipsets
have the cache connected to the standard memory bus.

 The Memory Bus:

 Second-level system bus that connects the memory subsystem to the chipset
and the processor.
+ 10

Bus Hierarchy

 The Local I/O Bus (High-speed I/O Bus)

 High-speed input/output bus used for connecting performance-critical
peripherals to the memory, chipset, and processor.
 For example, video cards, etc.
 The two most common local I/O buses are the VLB and PCI.

 The Standard I/O Bus

 Used for slower peripherals (mice, modems, regular sound cards, low-
speed networking) and also for compatibility with older devices.
 The Industry Standard Architecture (ISA) bus.
+ 11

Characteristics of Bus
 Bus Width
 The number of bits that can travel in parallel down the bus.
 The wider the bus, the more information can flow over the channel, as a
wider highway can carry more cars than a narrow one.
 The original ISA bus on the IBM PC was 8 bits wide; the universal
ISA bus used now is 16 bits. Other I/O buses (VLB and PCI) are 32 bits
wide.
 The memory and processor buses on Pentium and higher PCs are 64
bits wide.
 The address bus width can be specified independently of the data bus
width. The width of the address bus dictates how many different
memory locations that bus can transfer information to or from.
+ 12

Characteristics of Bus

 Bus Speed
 The speed of the bus reflects how many bits of information can be
sent across each wire each second.
 Analogy: (how fast the cars are driving on our analogical highway.)

 Most buses transmit one bit of data per line, per clock cycle,
although newer high-performance buses like AGP may actually
move two bits of data per clock cycle, doubling performance.
 Older buses like the ISA bus may take two clock cycles to move one
bit, halving performance
+ 13

Characteristics of Bus

 Bus Bandwidth
 Bandwidth, or throughput, refers to the total amount of data
that can theoretically be transferred on the bus in a given unit
of time.
 Analogy: On highway if the bus width is the number of
lanes, and the bus speed is how fast the cars are driving, then
the bandwidth is the product of these two and reflects the
amount of traffic that the channel can convey per second.
 Measured in bits per second or bytes per second.
 Bandwidth = bus width x bus speed.
 For very slow bus, bandwidth = ½ (bus width x bus speed)
+
Peripheral Component Interconnect
(PCI)
 A popular high bandwidth, processor independent bus that can function
as a mezzanine or peripheral bus

 Delivers better system performance for high speed I/O subsystems

 PCI Special Interest Group (SIG)

 Created to develop further and maintain the compatibility of the PCI
specifications

 PCI Express (PCIe)

 Point-to-point interconnect scheme intended to replace bus-based schemes such as
PCI
 Key requirement is high capacity to support the needs of higher data rate I/O
devices, such as Gigabit Ethernet
 Another requirement deals with the need to support time dependent data streams

Adapted from © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
 Core Core

Gigabit PCIe
Memory
Ethernet
Chipset
PCIe–PCI PCIe
Memory
Bridge

PCIe

PCIe PCIe
Switch

PCIe PCIe

Legacy PCIe PCIe PCIe

endpoint endpoint endpoint endpoint

Fig u re 3 . 2 1 Ty p ic a l Co n fig u ra t io n Us in g P CI e

Adapted from © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+ Summary
Bus Systems

Chapter 5

 Bus interconnection
 Data Bus
 Address Bus
 Control Bus
Bus hierarchy
Characteristics of bus
PCI and PCI express

Adapted from © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.