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buses

The document outlines the interconnection structure of computer modules, detailing the connections required for memory, input/output, and CPU. It describes various bus architectures, including data, address, and control buses, along with their functions and performance implications. Additionally, it covers bus standards and types, highlighting the differences between centralized and distributed arbitration methods.

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mfarrukhnadeem1
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12 views23 pages

buses

The document outlines the interconnection structure of computer modules, detailing the connections required for memory, input/output, and CPU. It describes various bus architectures, including data, address, and control buses, along with their functions and performance implications. Additionally, it covers bus standards and types, highlighting the differences between centralized and distributed arbitration methods.

Uploaded by

mfarrukhnadeem1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1

Connecting
• All the units must be connected
(the collection of paths connecting the various modules is
called interconnection structure)
• Different type of connection for different
type of unit
—Memory
—Input/Output
—CPU
Bus Architecture
• Address:
—If I/O, a value between 0000H and FFFFH is
issued.
—If memory, it depends on the architecture:
– 20 -bits (8086/8088)
– 24 -bits (80286/80386SX)
– 25 -bits (80386SL/SLC/EX)
– 32 -bits (80386DX/80486/Pentium)
– 36 -bits (Pentium Pro/II/III)
Computer Modules
Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
—Read
—Write
—Timing
Input/Output Connection(1)
• Similar to memory from computer’s
viewpoint
• Output
—Receive data from computer
—Send data to peripheral
• Input
—Receive data from peripheral
—Send data to computer
Input/Output Connection(2)
• Receive control signals from computer
• Send control signals to peripherals
—e.g. spin disk
• Receive addresses from computer
—e.g. port number to identify peripheral
• Send interrupt signals (control)
CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
Buses
• There are a number of possible
interconnection systems
• Single and multiple BUS structures are
most common
• e.g. Control/Address/Data bus (PC)
• e.g. Unibus (DEC-PDP)
What is a Bus?
• A communication pathway connecting two
or more devices
• Usually broadcast
• Often grouped
—A number of channels in one bus
—e.g. 32 bit data bus is 32 separate single bit
channels
• Power lines may not be shown
Data Bus
• Carries data
—Remember that there is no difference between
“data” and “instruction” at this level
• Width is a key determinant of
performance
—8, 16, 32, 64 bit
Address bus
• Identify the source or destination of data
• e.g. CPU needs to read an instruction
(data) from a given location in memory
• Bus width determines maximum memory
capacity of system
—e.g. 8080 has 16 bit address bus giving 64k
address space
Control Bus
• Control and timing information
—Memory read/write signal
—Interrupt request
—Clock signals
Bus Interconnection Scheme
Big and Yellow?
• What do buses look like?
—Parallel lines on circuit boards
—Ribbon cables
—Strip connectors on mother boards
– e.g. PCI
—Sets of wires
Physical Realization of Bus Architecture
Single Bus Problems
• Lots of devices on one bus leads to:
—Propagation delays
– Long data paths mean that co-ordination of bus use
can adversely affect performance
– If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to
overcome these problems
Traditional (bus architecture)
(with cache)
High Performance Bus
Bus Types
• Dedicated
—Separate data & address lines
• Multiplexed
—Shared lines
—Address valid or data valid control line
—Advantage - fewer lines
—Disadvantages
– More complex control
– Ultimate performance
Centralised or Distributed Arbitration
• Centralised
—Single hardware device controlling bus access
– Bus Controller
– Arbiter
—May be part of CPU or separate
• Distributed
—Each module may claim the bus
—Control logic on all modules
Bus Standards
• ISA (Industry Standard Architecture): 8 MHz
— 8-bit (8086/8088)
— 16-bit (80286-Pentium)
• EISA : 8 MHz
— 32-bit (older 386 and 486 machines).
• PCI (Peripheral Component Interconnect):
— 33 MHz 32-bit or 64-bit (Pentiums)
• VESA (Video Electronic Standards Association):
— 32-bit or 64-bit (Pentiums), Runs at processor speed.
— Only disk and video. Competes with the PCI but is not
popular.
Bus Standards
• USB (Universal Serial Bus):
— 12 Mbps / 480 Mbps, Serial connection to
microprocessor.
— For keyboards, the mouse, modems and sound cards.
To reduce system cost through fewer wires.
• IEEE 1394
— 400 Mbps, primary target is audio/visual consumer
electronic devices
• AGP (Advanced Graphics Port): 66MHz
— 64-bits for 533MB/sec, Fast parallel connection, video
cards. To accommodate the new DVD
(Digital Versatile Disk) players.

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