Digital System Design

Verilog® HDL
Behavioral Modeling (1)

Maziar Goudarzi
Today program

Behavioral Modeling
Concepts
Constructs

2005 Verilog HDL 2

Introduction

The move toward higher abstractions

Gate-level modeling
Netlist of gates
Dataflow modeling
Boolean function assigned to a net
Now, behavioral modeling
A sequential algorithm (quite similar to software) that
determines the value(s) of signal(s)

2005 Verilog HDL 3

Structured Procedures
 Two basic structured procedure statements
always
initial
All behavioral statements can appear only inside these
blocks
Each always or initial block has a separate activity flow
(concurrency)
Start from simulation time 0
Cannot be nested

2005 Verilog HDL 4

Structured Procedures:
initial statement
 Starts at time 0
 Executes only once during a simulation
 Multiple initial blocks, execute in parallel
All start at time 0
Each finishes independently
 Syntax:
initial
begin
// behavioral statements
end

2005 Verilog HDL 5

Structured Procedures:
initial statement (cont’d)
 Example:
module stimulus;
initial
reg x, y, a, b, m;
#50 $finish;
endmodule
initial
m= 1’b0;

initial
begin
#5 a=1’b1;
#25 b=1’b0;
end

initial
begin
#10 x=1’b0;
#25 y=1’b1;
end

2005 Verilog HDL 6

Structured Procedures:
always statement
 Start at time 0
 Execute the statements in a looping fashion
 Example
module clock_gen;
reg clock;

// Initialize clock at time zero

initial Can we move this to
clock = 1’b0; the always block?

// Toggle clock every half-cycle (time period =20)

always
#10 clock = ~clock;

initial
What happens if such a
#1000 $finish; $finish is not included?
endmodule
2005 Verilog HDL 7
Procedural Assignments

Assignments inside initial and always

Are used to update values of reg,
integer, real, or time variables
The value remains unchanged until another
procedural assignment updates it
In contrast to continuous assignment (Dataflow
Modeling, previous chapter)

2005 Verilog HDL 8

Procedural Assignments (cont’d)
 Syntax
 <lvalue> = <expression>

 <lvalue> can be
 reg, integer, real, time
 A bit-select of the above (e.g., addr[0])
 A part-select of the above (e.g., addr[31:16])
 A concatenation of any of the above
 <expression> is the same as introduced in dataflow modeling
 What happens if the widths do not match?
 LHS wider than RHS => RHS is zero-extended
 RHS wider than LHS => RHS is truncated (Least significant part is kept)

2005 Verilog HDL 9

Behavioral Modeling Statements:
Conditional Statements
 Just the same as if-else in C
 Syntax:
if (<expression>) true_statement;

if (<expression>) true_statement;
else false_statement;

if (<expression>) true_statement1;
else if (<expression>) true_statement2;
else if (<expression>) true_statement3;
else default_statement;

 True is 1 or non-zero
 False is 0 or ambiguous (x or z)
 More than one statement: begin end

2005 Verilog HDL 10

Conditional Statements (cont’d)
 Examples:
if (!lock) buffer = data;

if (enable) out = in;

if (number_queued < MAX_Q_DEPTH)

begin
data_queue = data;
number_queued = number_queued +1;
end
else $display(“Queue full! Try again.”);

if (alu_control==0)
y = x+z;
else if (alu_control==1)
y = x-z;
else if (alu_control==2)
y = x*z;
else
$display(“Invalid ALU control signal.”);

2005 Verilog HDL 11

Behavioral Modeling Statements:
Multiway Branching
 Similar to switch-case statement in C
 Syntax:
case (<expression>)
alternative1: statement1;
alternative2: statement2;
...
default: default_statement; // optional
endcase
 Notes:
<expression> is compared to the alternatives in the
order specified.
Default statement is optional
2005 Verilog HDL 12
Multiway Branching (cont’d)
 Examples:
reg [1:0] alu_control;
...
case (alu_control)
2’d0: y = x + z;
2’d1: y = x – z;
2’d2: y = x * z;
default: $display(“Invalid ALU control signal.”);

 Now, you write a 4-to-1 multiplexer.

2005 Verilog HDL 13

Multiway Branching (cont’d)
 Example 2:
module mux4_to_1(out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3, s1, s0;
reg out;

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1,s0})
2’d0: out = i0;
2’d1: out = i1;
2’d2: out = i2;
2’d3: out = i3;
endcase
endmodule

2005 Verilog HDL 14

Multiway Branching (cont’d)
 The case statements compares <expression> and alternatives bit-for-bit
 x and z values should match
module demultiplexer1_to_4(out0, out1, out2, out3, in, s1, s0);
output out0, out1, out2, out3;
input in, s1, s0;
always @(s1 or s0 or in)
case( {s1, s0} )
2’b00: begin ... end
2’b01: begin ... end
2’b10: begin ... end
2’b11: begin ... end
2’bx0, 2’bx1, 2’bxz, 2’bxx, 2’b0x, 2’b1x, 2’bzx:
begin ... end
2’bz0, 2’bz1, 2’bzz, 2’b0z, 2’b1z:
begin ... end
default: $display(“Unspecified control signals”);
endcase
endmodule

2005 Verilog HDL 15

Multiway Branching (cont’d)
 casex and casez keywords
 casez treats all z values as “don’t care”
 casex treats all x and z values as “don’t care”
 Example:
reg [3:0]
integer state;
casex(encoding)
4’b1xxx: next_state=3;
4’bx1xx: next_state=2;
4’bxx1x: next_state=1;
4’bxxx1: next_state=0;
default: next_state=0;
endcase
2005 Verilog HDL 16
Behavioral Modeling Statements:
Loops
Loops in Verilog
while, for, repeat, forever
The while loop syntax:
while (<expression>)
statement;
Example:
Look at p. 136 of your book

2005 Verilog HDL 17

Loops (cont’d)

The for loop

Similar to C
Syntax:
for( init_expr; cond_expr; change_expr)
statement;
Example:
Look at p. 137 of your book

2005 Verilog HDL 18

Loops (cont’d)

The repeat loop

Syntax:
repeat( number_of_iterations )
statement;
The number is evaluated only when the loop is
first encoutered
Example:
Look at p. 138 of your book

2005 Verilog HDL 19

Loops (cont’d)

The forever loop

Syntax:
forever
statement;
Equivalent to while(1)
Example:
Look at pp. 139-140 of your book

2005 Verilog HDL 20

Procedural Assignments (cont’d)
 The two types of procedural assignments
 Blocking assignments
 Non-blocking assignments
 Blocking assignments
 are executed in order (sequentially)
 Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count; All executed at time 0
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
#15 reg_a[2] = 1’b1; executed at time 15
#10 reg_b[15:13] = {x, y, z};
count = count + 1;
2005 end Verilog HDL 21
All executed at time 25
Procedural Assignments (cont’d)
 Non-blocking assignments
 The next statements are not blocked for this one
 Syntax:
 <lvalue> <= <expression>
 Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count; All executed at time 0
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
reg_a[2] <= #15 1’b1; Scheduled to run at time 15
reg_b[15:13] <= #10 {x, y, z};
count <= count + 1; Scheduled to run at time 10
2005
end Verilog HDL 22
Procedural Assignments (cont’d)
 Application of non-blocking assignments
Used to model concurrent data transfers
Example: Write behavioral statements to swap values of
two variables
Another example
always @(posedge clock)
begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1;
end
The old value of reg1 is used

2005 Verilog HDL 23

Procedural Assignments (cont’d)
 Race condition
 When the final result of simulating two (or more) concurrent
processes depends on their order of execution
 Example:
always @(posedge clock)
b = a;
always @(posedge clock)
a = b;
 Solution: always @(posedge clock)
begin
always @(posedge clock) temp_b = b;
b <= a; temp_a = a;
always @(posedge clock) b = temp_a;
a = temp_b;
a <= b; end
2005 Verilog HDL 24
Procedural Assignments (cont’d)

Recommendation
Concurrent data transfers => race condition
Use non-blocking assignments wherever
concurrent data transfers
Example: pipeline modeling
Disadvantage:
Lower simulation performance
Higher memory usage in the simulator

2005 Verilog HDL 25

What we learned today
 What is behavioral modeling
 What are the Verilog constructs for behavioral
modeling
 Statements used in behavioral modeling
Procedural assignment
 Blocking vs. non-blocking
Conditional
Multiway branching
Loops

2005 Verilog HDL 26

Other Notes

Homework 5
Chapter 7 exercises 1-4, 10, 12, 13, 14, 15
Due date: Next Sunday (Azar 6th)

2005 Verilog HDL 27