Lecture #4: Lo'ai Tawalbeh

Chapter 4:
Lo’ai Tawalbeh
Lecture #4
Register Transfer and Microoperations
23/2/2006
cpe 252: Computer Organization 1

contents
• Register Transfer Language
• Register Transfer
• Bus and Memory Transfers
• Arithmetic Microoperations
• Logic Microoperations
• Shift Microoperations
• Arithmetic Logic Shift Unit

4-1 Register Transfer Language
(RTL)
• Digital System: An interconnection of hardware
modules that do a certain task on the
information.
• Registers + Operations performed on the data
stored in them = Digital Module
• Modules are interconnected with common data
and control paths to form a digital computer
system

4-1 Register Transfer Language cont.
• Microoperations: operations executed on data
stored in one or more registers.
• For any function of the computer, a sequence of
microoperations is used to describe it
• The result of the operation may be:
– replace the previous binary information of a
register or
– transferred to another register
Shift Right Operation
101101110011 010110111001

• The internal hardware organization of a
digital computer is defined by specifying:
• The set of registers it contains and their function
• The sequence of microoperations performed on
the binary information stored in the registers
• The control that initiates the sequence of
microoperations
• Registers + Microoperations Hardware + Control
Functions = Digital Computer

• Register Transfer Language (RTL) : a
symbolic notation to describe the microoperation
transfers among registers
Next steps:
– Define symbols for various types of microoperations,
– Describe the hardware that implements these
microoperations

4-2 Register Transfer (our first
microoperation)
• Computer registers are designated by

capital letters (sometimes followed by
numerals) to denote the function of the
register
• R1: processor register
• MAR: Memory Address Register (holds an address
for a memory unit)
• PC: Program Counter
• IR: Instruction Register
• SR: Status Register
4-2 Register Transfer cont.
• The individual flip-flops in an n-bit register

are numbered in sequence from 0 to n-1
(from the right position toward the left
position)
R1 7 6 5 4 3 2 1 0
Register R1 Showing individual bits
A block diagram of a register

Other ways of drawing the block diagram of a register:
15 0
PC
Numbering of bits
15 87 0
Upper byte PC(H) PC(L) Lower byte
Partitioned into two parts

• Information transfer from one register to another is
described by a replacement operator: R2 ← R1
• This statement denotes a transfer of the content of
register R1 into register R2
• The transfer happens in one clock cycle
• The content of the R1 (source) does not change
• The content of the R2 (destination) will be lost and
replaced by the new data transferred from R1
• We are assuming that the circuits are available from the
outputs of the source register to the inputs of the
destination register, and that the destination register has
a parallel load capability

• Conditional transfer occurs only under a
control condition
• Representation of a (conditional) transfer

P: R2 ← R1
• A binary condition (P equals to 0 or 1)
determines when the transfer occurs
• The content of R1 is transferred into R2
only if P is 1

Hardware implementation of a controlled transfer: P: R2 ← R1

Block diagram: Control P Load
R2 Clock
Circuit
R1
t t+1
Timing diagram
Clock
Synchronized
Load
with the clock
Transfer occurs here

Basic Symbols for Register Transfers

Symbol Description Examples
Letters & Denotes a register MAR, R2
numerals
Parenthesis ( ) Denotes a part of a R2(0-7), R2(L)
register
Arrow ← Denotes transfer of R2 ← R1
information
Comma , Separates two R2 ← R1, R1 ← R2
microoperations
4-3 Bus and Memory Transfers
• Paths must be provided to transfer information
from one register to another
• A Common Bus System is a scheme for
transferring information between registers in a
multiple-register configuration
• A bus: set of common lines, one for each bit of a
register, through which binary information is
transferred one at a time
• Control signals determine which register is
selected by the bus during each particular
register transfer

Register A Register B Register C Register D
Bus lines
Register D Register C Register B Register A

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
D3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A 2 A 1 A 0
D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0
3 2 1 0 3 2 1 0 3 2 1 0
3 2 1 0 S0
S0 S0 S0
MUX3 MUX2 MUX1 MUX0 S1
S1 S1 S1
4-Line Common Bus

• The transfer of information from a bus into one of
many destination registers is done:
– By connecting the bus lines to the inputs of all destination
registers and then:
– activating the load control of the particular destination
register selected
• We write: R2 ← C to symbolize that the content of
register C is loaded into the register R2 using the
common system bus
• It is equivalent to: BUS ←C, (select C)
R2 ←BUS (Load R2)

4-3 Bus and Memory Transfers:
Three-State Bus Buffers
• A bus system can be constructed with
three-state buffer gates instead of
multiplexers
• A three-state buffer is a digital circuit that
exhibits three states: logic-0, logic-1, and
high-impedance (Hi-Z) Control input C
Normal input A Output B
Three-State Buffer
Three-State Bus Buffers cont.
C=1
Buffer
A B A B
C=0
Open Circuit
A B A B

Three-State Bus Buffers cont.
S1 0
Select
S0 1
Bus line for bit 0
2×4 A0
Decoder 2
Enable E
3
B0
C0
Bus line with three-state

buffer (replaces MUX0 in the
previous diagram) D0

Memory Transfer
• Memory read : Transfer from memory
• Memory write : Transfer to memory
• Data being read or wrote is called a memory word
(called M)- (refer to section 2-7)
• It is necessary to specify the address of M when
writing /reading memory
• This is done by enclosing the address in square
brackets following the letter M
• Example: M[0016] : the memory contents at
address 0x0016
Memory Transfer cont.
• Assume that the address of a memory unit
is stored in a register called the Address
Register AR
• Lets represent a Data Register with DR,
then:
• Read: DR ← M[AR]
• Write: M[AR] ← DR

Memory Transfer cont.
AR
x0C 19
x12 x0E 34
R1 x10 45
100 x12 66
x14 0
x16 13
R1←M[AR] x18 22
RAM
R1 R1
100 66

4-4 Arithmetic Microoperations
• The microoperations most often
encountered in digital computers are
classified into four categories:
– Register transfer microoperations
– Arithmetic microoperations (on numeric data
stored in the registers)
– Logic microoperations (bit manipulations on
non-numeric data)
– Shift microoperations
4-4 Arithmetic Microoperations cont.
• The basic arithmetic microoperations are:
addition, subtraction, increment,
decrement, and shift
• Addition Microoperation:
R3 ←R1+R2
• Subtraction Microoperation:
R3 ←R1-R2 or : 1’s complement
R3 ←R1+R2+1
4-4 Arithmetic Microoperations cont.
• One’s Complement Microoperation:
R2 ←R2
• Two’s Complement Microoperation:
R2 ←R2+1
• Increment Microoperation:
R2 ←R2+1
• Decrement Microoperation:
R2 ←R2-1
Half Adder/Full Adder
Half Adder x y c s x
0 0 0 0 c = xy s = xy’ + x’y c
=x  y y
0 1 0 1
1 0 0 1 s
1 1 1 0
Full Adder
y y
x y cn-1 cn s
0 0 0 0 0 0 0 0 1
0 0 1 0 1 0 1 c 1 0 cn-1
n-1
0 1 0 0 1 x 1 1 x 0 1
0 1 1 1 0 0 1 1 0
1 0 0 0 1 cn s
1 0 1 1 0
1 1 0 1 0 cn = xy + xcn-1+ ycn-1
1 1 1 1 1 = xy + (x  y)cn-1
x s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1
y S = x  y  cn-1 = (x  y)  cn-1
cn-1
cn
Binary Adder
B3 A3 B2 A2 B1 A1 B0 A0
C3 C2 C1
FA FA FA FA C0
C4 S3 S2 S1 S0
4-bit binary adder

(connection of FAs)

Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0
C3 C2 C1 C0
FA FA FA FA
C4 S3 S2 S1 S0
4-bit adder-subtractor

Binary Adder-Subtractor
• For unsigned numbers, this gives A – B if A≥B or the 2’s complement of (B – A) if A <
B
(example: 3 – 5 = -2= 1110)
• For signed numbers, the result is A – B provided that there is no overflow. (example :
-3 – 5= -8) 1101
1011 +
‫ـــــــــــــــــــــــــــ‬
1000
C3 1, if overflow
=V
C4 0, if no overflow
Overflow detector for signed numbers

Binary Adder-Subtractor cont.
• What is the range of unsigned numbers
that can be represented in 4 bits?
• What is the range of signed numbers that
can be represented in 4 bits?
• Repeat for n-bit?!

Binary Incrementer
A3 A2 A1 A0 1
x y x y x y x y
HA HA HA HA
C S C S C S C S
C4 S3 S2 S1 S0
4-bit Binary Incrementer

Binary Incrementer
• Binary Incrementer can also be
implemented using a counter
• A binary decrementer can be implemented
by adding 1111 to the desired register
each time!

Arithmetic Circuit
• This circuit performs seven distinct
arithmetic operations and the basic
component of it is the parallel adder
• The output of the binary adder is
calculated from the following arithmetic
sum:
• D = A + Y + Cin

Arithmetic Circuit cont.
A3 A2 A1 A0
1 0 B 3 B3 S 1 S 0 1 0 B2 B 2 S 1 S0 1 0 B1 B 1 S 1 S0 1 0 B 0 B0 S 1 S 0
3 2 1 0 S 1 S0 3 2 1 0 S 1 S0 3 2 1 0 S 1 S0 3 2 1 0 S 1 S0
4×1 MUX 4×1 MUX 4×1 MUX 4×1 MUX Figure A
Y3 X3 Y2 X2 Y1 X1 Y0 X0
C3 C2 C1
FA FA FA FA Cin
Cout D3 D2 D1 D0
4-bit Arithmetic Circuit

4-5 Logic Microoperations
The four basic microoperations
OR Microoperation
• Symbol: , +
• Gate:
• Example: 1001102  10101102 = 11101102

OR OR
P+Q: R1←R2+R3, R4←R5 R6

cpe 252: Computer Organization
ADD 35
cont.
AND Microoperation
• Symbol: 
• Gate:
• Example: 1001102  10101102 = 00001102

cont.
Complement (NOT) Microoperation
• Symbol: 
• Gate:
• Example: 10101102 = 01010012

cont.
XOR (Exclusive-OR) Microoperation
• Symbol: 
• Gate:
• Example: 1001102  10101102 =

11100002

Other Logic Microoperations
Selective-set Operation
• Used to force selected bits of a register
into logic-1 by using the OR operation
• Example: 01002  10002 = 11002

Loaded into a register from
In a processor register
memory to perform the
selective-set operation

Other Logic Microoperations cont.
Selective-complement (toggling) Operation
• Used to force selected bits of a register to be
complemented by using the XOR operation
• Example: 00012  10002 = 10012
Loaded into a register from

In a processor register
memory to perform the
selective-complement operation

Insert Operation
• Step1: mask the desired bits
• Step2: OR them with the desired value
• Example: suppose R1 = 0110 1010, and we

desire to replace the leftmost 4 bits (0110) with
1001 then:
– Step1: 0110 1010  0000 1111
– Step2: 0000 1010  1001 0000
 R1 = 1001 1010
NAND Microoperation
• Symbols:  and 
• Gate:
• Example: 1001102  10101102 = 11110012

NOR Microoperation
• Symbols:  and 
• Gate:
• Example: 1001102  10101102 = 00010012

Set (Preset) Microoperation
• Force all bits into 1’s by ORing them with a value
in which all its bits are being assigned to logic-1
• Example: 1001102  1111112 = 1111112
Clear (Reset) Microoperation
• Force all bits into 0’s by ANDing them with a
value in which all its bits are being assigned to
logic-0
• Example: 1001102  0000002 = 0000002

Hardware Implementation
• The hardware implementation of logic
microoperations requires that logic gates
be inserted for each bit or pair of bits in the
registers to perform the required logic
function
• Most computers use only four (AND, OR,
XOR, and NOT) from which all others can
be derived.

Hardware Implementation cont.
S1
4×1 Operatio
S0
MUX S1 S0 Output n
Ai
0 0 E=AB XOR
Bi
0
0 1 E=AB OR
1 0 E=AB AND
1 Ei
1 1 E=A Complem
ent
3 This is for one bit i
Figure B cpe 252: Computer Organization 46

4-6 Shift Microoperations
• Used for serial transfer of data
• Also used in conjunction with arithmetic, logic,
and other data-processing operations
• The contents of the register can be shifted to the
left or to the right
• As being shifted, the first flip-flop receives its
binary information from the serial input
• Three types of shift: Logical, Circular, and
Arithmetic

4-6 Shift Microoperations cont.
Serial Input r2 Serial Output

rn-1 r3 r1 r0
Determines Shift Right

the “shift”
type
Serial Output Serial Input

rn-1 r3 r2 r1 r0
Shift Left
**Note that the bit ri is the bit at position (i) of the register

4-6 Shift Microoperations:
Logical Shifts
• Transfers 0 through the serial input
• Logical Shift Right: R1←shr R1
The same
• Logical Shift Left: R2←shl R2

The same
? rn-1 r3 r2 r1 r0 0
Logical Shift Left

4-6 Shift Microoperations:
Circular Shifts (Rotate Operation)
• Circulates the bits of the register around
the two ends without loss of information
• Circular Shift Right: R1←cir R1
The same
• Circular Shift Left: R2←cil R2

The same
rn-1 r3 r2 r1 r0
Circular Shift Left

Arithmetic Shifts
• Shifts a signed binary number to the left or right
• An arithmetic shift-left multiplies a signed binary
number by 2: ashl (00100): 01000
• An arithmetic shift-right divides the number by 2
ashr (00100) : 00010
• An overflow may occur in arithmetic shift-left,
and occurs when the sign bit is changed (sign
reversal)

Arithmetic Shifts cont.
rn-1 r3 r2 r1 r0
?
Sign Arithmetic Shift Right

Bit
? rn-1 r3 r2 r1 r0 0
Sign
Arithmetic Shift Left
Bit

Arithmetic Shifts cont.
• An overflow flip-flop Vs can be used to detect
an arithmetic shift-left overflow
Vs = Rn-1  Rn-2
Rn-1 1  overflow
Vs =
Rn-2 0  no overflow

4-6 Shift Microoperations cont.
• Example: Assume R1=11001110, then:

– Arithmetic shift right once : R1 = 11100111
– Arithmetic shift right twice : R1 = 11110011
– Arithmetic shift left once : R1 = 10011100
– Arithmetic shift left twice : R1 = 00111000
– Logical shift right once : R1 = 01100111
– Logical shift left once : R1 = 10011100
– Circular shift right once : R1 = 01100111
– Circular shift left once : R1 = 10011101
• A possible choice for a shift unit would be
a bidirectional shift register with parallel
load (refer to Fig 2-9). Has drawbacks:
– Needs two pulses (the clock and the shift
signal pulse)
– Not efficient in a processor unit where multiple
number of registers share a common bus
• It is more efficient to implement the shift
operation with a combinational circuit
Serial Input IR Serial Input IL
A3A2 A1 A0
Select
S 1 0 S 1 0 S 1 0 S 1 0 0 for shift right

1 for shift left
MUX MUX MUX MUX
H3 H2 H1 H0
4-bit Combinational Circuit Shifter

4-7 Arithmetic Logic Shift Unit
• Instead of having individual registers
performing the microoperations directly,
computer systems employ a number of
storage registers connected to a common
operational unit called an Arithmetic Logic
Unit (ALU)

4-7 Arithmetic Logic Shift Unit cont.
S3
S2
S1 Ci
S0
One stage of Di
arithmetic
circuit (Fig.A)
Select
One stage of Fi
ALU Ci+1 0 4×1
1 MUX
One stage of Ei 2
logic circuit
Bi (Fig.B) 3
Ai
shr
Ai+1
shl
Ai-1

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Chapter 4:

Register Transfer and Microoperations

cpe 252: Computer Organization 1

• Register Transfer Language

• Bus and Memory Transfers

• Arithmetic Logic Shift Unit

cpe 252: Computer Organization 2

cpe 252: Computer Organization 3

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• Computer registers are designated by

• The individual flip-flops in an n-bit register

Register R1 Showing individual bits

A block diagram of a register

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Other ways of drawing the block diagram of a register:

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• Representation of a (conditional) transfer

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Hardware implementation of a controlled transfer: P: R2 ← R1

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Basic Symbols for Register Transfers

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Register D Register C Register B Register A

4-Line Common Bus

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Normal input A Output B

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Bus line with three-state

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4-bit binary adder

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Overflow detector for signed numbers

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4-bit Binary Incrementer

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4×1 MUX 4×1 MUX 4×1 MUX 4×1 MUX Figure A

4-bit Arithmetic Circuit

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• Example: 1001102  10101102 = 11101102

P+Q: R1←R2+R3, R4←R5 R6

• Example: 1001102  10101102 = 00001102

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• Example: 10101102 = 01010012

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• Example: 1001102  10101102 =

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• Example: 01002  10002 = 11002

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• Example: 00012  10002 = 10012

Loaded into a register from