3D IC Technology: Vinod Chauhan 108170

3D IC technology
VINOD CHAUHAN
108170
What is a 3D IC?
Could be Heterogeneous… “Stacked” 2D (Conventional) ICs

Motivation
 Interconnect structures increasingly consume more of the power
and delay budgets in modern design
 Plausible solution: increase the number of “nearest neighbors” seen
by each transistor by using 3D IC design
 Smaller wire cross-sections and longer lines to traverse larger chips
increase RC delay.
 RC delay is increasingly becoming the dominant factor
 At 250 nm Cu was introduced alleviate the adverse effect of
increasing interconnect delay.
 130 nm technology node, substantial interconnect delays will result.
Performance Characteristics
 Timing
 Energy
 With shorter interconnects in 3D ICs, both switching
energy and cycle time are expected to be reduced
Timing
 In current technologies, timing is
interconnect driven.
 Reducing interconnect length in
designs can dramatically reduce
RC delays and increase chip
performance
 The graph below shows the
results of a reduction in wire
length due to 3D routing.
Energy performance
 Wire length reduction has an impact on
the cycle time and the energy dissipation
 Energy dissipation decreases with the
number of layers used in the design
OVERVIEW OF 3-D IC
TECHNOLOGY
#Beam Re crystallization
Advantage:
1. MOS transistors fabricated on poly silicon
exhibit very low surface mobility values [of the
order of 10 cm/Vs].
2. MOS transistors fabricated on poly silicon have
high threshold
Disadvantage:
1. This technique, however, may not be very
practical for 3-D devices because of the high
temperature involved during melting of the poly
silicon.
2. Difficulty in controlling the grain size
variations.
#PROCESSED WAFER BONDING:

Advantage:
1.Devices on equal active level have similar
electrical property.
2.Since all chips are fabricated separately and later
bonded ,there is independence of processing
temperature.
Disadvantage:
1.The lack of precision restricts the inter chip
communication to global metal lines.
# SILICON EPITAXIAL GROWTH
Advantage:
1.The quality of devices fabricated on these
epitaxial layer can be as good as those fabricated
underneath on the seed wafer surface, since the
grown layer is single crystal with few defects.
Disadvantage

The high temperatures involved in this process
cause significant degradation in the quality of
devices on lower layers.
Concerns in 3D circuit
 Thermal Issues in 3D-circuits
 EMI
 Reliability Issues
Thermal Issues in 3D Circuits
 Thermal Effects dramatically impact interconnect and device reliability in 2D

circuits.
 Due to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharp
increase in power density.
 Analysis of Thermal problems in 3D is necessary to evaluate thermal robustness of
different 3D technology and design options.
Heat Flow in 2D
Heat generated arises due to switching In 2D circuits we have only one layer of
Si to consider.
Heat Flow in 3D
With multi-layer circuits , the upper layers will also generate a significant fraction
of the heat. Heat increases linearly with level increase.
Heat Dissipation
 All active layers will be insulated from each other by layers of dielectrics
 With much lower thermal conductivity than Si
 Therefore heat dissipation in 3D circuits can accelerate many failure
mechanisms.
EMI in 3D ICs
 Interconnect Coupling Capacitance
 Coupling between the top layer metal of the first active layer and the device on
the second active layer devices is expected
EMI
 Interconnect Inductance Effects
 Shorter wire lengths help reduce the
inductance
 Presence of second substrate close to global
wires might help lower inductance by
providing shorter return paths
Reliability Issues?
 Electro thermal and Thermo-mechanical effects
between various active layers can influence electro-
migration and chip performance.
 Die yield issues may arise due to mismatches
between die yields of different layers, which affect
net yield of 3D chips.
Implications on Circuit Design
and Architecture
 Buffer Insertion
 Layout of Critical Paths
 Microprocessor Design
 Mixed Signal IC’s
 Physical design and Synthesis
Buffer Insertion
 Buffer Insertion
 Use of buffers in 3D circuits to break up long interconnects
 At top layers inverter sizes 450 times min inverter size for the relevant
technology
 These top layer buffers require large routing area and can reach up to
10,000 for high performance designs in 100nm technology
 With 3D technology repeaters can be placed on the second layer and
reduce area for the first layer.
Layout of Critical Paths and
Microprocessor Design
 Once again interconnect delay dominates in 2D
design.
 Logic blocks on the critical path need to
communicate with each other but due to placement
and design constraints are placed far away from
each other.
 With a second layer of Si these devices can be
placed on different layes of Si and thus closer to
each other using(VILICs)
 In Microprocessor design most critical paths

involve on chip caches on the critical path.
 Computational modules which access the cache
are distributed all over the chip while the cache is
in the corner.
 Cache can be placed on a second layer and
connected to these modules using (VILICs)
Mixed Signal ICs and Physical
Design
 Digital signals on chip can couple and interfere with
RF signals
 With multiple layers RF portions of the system can be
separated from their digital counterparts.
 Physical Design needs to consider the multiple layers
of Silicon available.
 Placement and routing algorithms need to be
modified
APPLICATIONS OF 3D Ics:
1.Portable Digital Electronic Camera
2.Digital Aodio Player
3.Smart Cellular Phone
4.Handheld Gaming Devices
Conclusion
 3D IC design is a relief to interconnect
driven IC design.
 Still many manufacturing and
technological difficulties
 Needs strong EDA applications for
automated design

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3D IC technology

Could be Heterogeneous… “Stacked” 2D (Conventional) ICs

#PROCESSED WAFER BONDING:

 Thermal Effects dramatically impact interconnect and device reliability in 2D

 In Microprocessor design most critical paths

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