EE40 Lec 20

MOS Circuits

Reading: Chap. 12 of Hambley

Supplement reading on MOS Circuits
http://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/EE40_MOS_Circuit.pdf

EE40 Fall 2009 Slide 1 Prof. Cheung

 OUTLINE
–Bias circuits
–Small-signal equivalent circuits
–Examples:
Common source amplifier
Source follower
Common gate amplifier
–Digital Gates
–CMOS

EE40 Fall 2009 Slide 2 Prof. Cheung

 Bias Circuits
• Use load line to find Quiescent operating point.
• Remember no current flow through the gate.
Fixed-plus Self-Bias CKT
VDD VDD

RD RD
R1
VG+vin

R2
RS

EE40 Fall 2009 Slide 3 Prof. Cheung

 Steps for MOSFET Circuit Analysis
• 1) Look at DC case to find Q point
– Use load line technique
– All capacitors are open circuit, Inductors are
short circuit
– Determine Q-point, get gm and rd for small
signal AC model
• 2) AC Small signal analysis
– DC source is ac ground (because there is no
AC signal variation).
– All capacitors are approximated as short
circuit (unless otherwise specified).
EE40 Fall 2009 Slide 4 Prof. Cheung
 Example: Common Source Amplifier

VDD

RD C
R1
+
C RL vo
VG -
+ +
v(t) vin R2
- RS C
-

EE40 Fall 2009 Slide 5 Prof. Cheung

 Step 1: find Q point

R2
VG  VDD VDD
R1  R2 Not connected
VGS  VG  I D RS for DC component

VDD  I D ( RD  RS )  VDS
RD C
R1
+
C VG RL vo
VDS -
+ +
v(t) vin R2
- RS C
-

Not connected
for DC component

EE40 Fall 2009 Slide 6 Prof. Cheung

 Load line to determine Q Point by graphical method

Loadline to determine VGSQ

VG  VGS
ID  VG  VGS
RS ID 
RS

VDD  VDS
ID 
R0  RS Loadline to determine VDSQ
VGSQ
VDD  VDS
ID 
R0  RS

From load lines, we get ID  and hence gm and rd

EE40 Fall 2009 Slide 7 Prof. Cheung
 Load line to determine Q Point by analytical method

Solve VGSQ assume saturation region first

VG  VGSQ
I DQ 
RS
I DQ  K ( VGSQ  V t ) 2

IDQ is known, then solve VDSQ

VDD  I DQ ( R D  R S )  VDSQ

Check VDSQ value is consistent with saturation region ( i.e. VDS> VGSQ-Vt)

From load lines, we get ID  and hence gm and rd

EE40 Fall 2009 Slide 8 Prof. Cheung
 Determination of gm and rd graphically
Example: Q point is known to be VGS=2.5V, VDS=6V

1 i D (2.9  2.3)mA
   0.05  103 Siemens
rd vDS (14  2)V
or rd  20k

EE40 Fall 2009 Slide 9 Prof. Cheung

 Determination of gm and rd by Analytical Models

In Saturation Region
i D  K ( v GS  Vt )2
KP W
K
i D 2 L
gm   2K ( v GS  Vt )  2 K i DQ   channel mod ulation factor
v GS
i D
1 / rd     i DQ
v DS

In Triode Region
i D  K[2( v GS  Vt ) v DS  v 2 DS ]
i D
gm   2Kv DSQ
v GS
i D
1 / rd   K[2( v GSQ  Vt )  2 v DSQ ]
v DS

EE40 Fall 2009 Slide 10 Prof. Cheung

 Small Signal Model

Inverting

vg  vin , vs  0  vgs  vin For output impedance Rout:

RL RD 1. Turn off all independent
vo  ( g m vgs ) sources.
RL  RD 2. Take away load impedance
vo RR RL
Av    gm L D vin  0, vgs  0, g m vgs  0
vin RL  RD
vin R1 R2 rd RD
Rin   Rout 
iin R1  R2 rd  RD
EE40 Fall 2009 Slide 11 Prof. Cheung
 Example: Source Follower

VDD

R1

C
VG C

+ + +
v(t) vin R2
- RS RL vo
-
-

EE40 Fall 2009 Slide 12 Prof. Cheung

 Step 1: find Q point
R2
VG  VDD VDD
R1  R2
VGS  VG  I D RS
VDD  I D RS  VDS
R1

C
VG C

+ + +
v(t) vin R2
- RS RL vo
-
-

EE40 Fall 2009 Slide 13 Prof. Cheung

 Small Signal Model

Non-inverting,
Voltage Gain 1
Rin high
Current gain can be high

1
RL  For output impedance Rout:
rd 1  RS 1  RL 1
1. Turn off all independent sources.
vgs  vin  vo
2. Take away RL
vo  g m vgs RL 3. Add Vx and find ix
vx  vs , vg  0, vgs  vx
vin  vgs (1  g m RL )

vo g m RL
Rs 
rd Rs
rd  Rs
v

, ix  x  g m (vx )  v x Rs1  g m
Rs

Av  
vin 1  g m RL 1
Rout 
v RR
Rin  in  1 2
g m  rd 1  Rs 1 Rout is small
iin R1  R2
EE40 Fall 2009 Slide 14 Prof. Cheung
 Example: Common Gate Amplifier

VDD

RD C

+
VG RL vo
-

+ + C
v(t) vin
- - RS
-VSS

EE40 Fall 2009 Slide 15 Prof. Cheung

 Step 1: find Q point

VDD
VGS  0  I D RS  VSS
VDD  VSS  I D ( RD  RS )  VDS
RD C

+
VG RL vo
-

+ + C
v(t) vin
- - RS
-VSS

EE40 Fall 2009 Slide 16 Prof. Cheung

 Load line

The only difference in all three circuits are the

intercepts at the axes.
Again from load lines, we get ID  and hence
gm and rd

EE40 Fall 2009 Slide 17 Prof. Cheung

 Small Signal Model

Non-inverting

1 For output impedance Rout:

RL 
RL 1  RD 1 1. Turn off all independent sources.
vgs  vin 2. Take away RL
vo   g m vgs RL 3. Add Vx and find ix
RRs
vo R 
Av   g m RL R  Rs
vin
vx
vgs ix   g m vgs
iin  ( g m vgs  ) RD
Rs
v 1 vgs   g m vgs R , but g m R  1 v gs  0
Rin  in 
iin g m  Rs 1 Rout  RD
EE40 Fall 2009 Slide 18 Prof. Cheung
 Logic Gates : Pull-Up and Pull-Down

PMOS or Resistor

NMOS or Resistor

EE40 Fall 2009 Slide 19 Prof. Cheung

 Inverter = NOT Gate

Vin Vout
Ideal Transfer Characteristics
Vout

Vin
V/2 V

EE40 Fall 2009 Slide 20 Prof. Cheung

 NMOS Inverter: Resistor Pull-Up
VDD
Circuit: Voltage-Transfer Characteristic
vOUT
RD
iD
VDD
+
F
A
+
vDS = vOUT
iD vIN
vIN = VDD
– –

vIN
0 VT VDD
VDD/RD

increasing
vGS = vIN > VT A F
0 1
1 0
0 vDS
vGS = vin  VT VDD
EE40 Fall 2009 Slide 21 Prof. Cheung
 NMOS NAND Gate

• Output is low only if both inputs are high

VDD

RD
F
A

Truth Table
A B F
B 0 0 1
0 1 1
1 0 1
1 1 0

EE40 Fall 2009 Slide 22 Prof. Cheung

 NMOS NOR Gate

• Output is low if either input is high

VDD

RD
F

A B
Truth Table
A B F
0 0 1
0 1 0
1 0 0
1 1 0

EE40 Fall 2009 Slide 23 Prof. Cheung

 Disadvantages of NMOS Logic Gates
• Large values of RD are required in order to
– achieve a low value of VLOW
– keep power consumption low

 Large resistors are needed, but these take

up a lot of space.

EE40 Fall 2009 Slide 24 Prof. Cheung

 CMOS Inverter: Intuitive Perspective

CIRCUIT SWITCH MODELS

VDD VDD VDD

G S
Rp
D
VIN VOUT VOUT VOUT
D VOL = 0 V VOH = VDD
G Rn
S

Low static power consumption, since

one MOSFET is always off in steady state VIN = VDD VIN = 0 V
EE40 Fall 2009 Slide 25 Prof. Cheung
 The CMOS Inverter: Current Flow
N: sat
VOUT P: sat i
N: off
VDD P: lin C
VDD
G S
N: sat
D P: lin
VIN I VOUT
D A B D E
G N: lin
S
P: sat
N: lin
P: off
0 VIN
0 VDD

EE40 Fall 2009 Slide 26 Prof. Cheung

 Power Dissipation: Direct-Path Current

VDD VDD
VDD-VT
S
vIN:
G

D VT
0
vIN i vOUT
D Ipeak
G
S
i:
0
tsc time
Energy consumed per switching period: Edp  t scVDD I peak
EE40 Fall 2009 Slide 27 Prof. Cheung
 CMOS NAND Gate
VDD A B F
0 0 1
0 1 1
1 0 1
1 1 0
A B Notice that the
pull-up network is
related to the pull-
F down network by
A DeMorgan’s
Theorem!
NMOS, Pull-down PMOS, Pull-up

EE40 Fall 2009 Slide 28 Prof. Cheung

 CMOS NOR Gate
VDD A B F
0 0 1
0 1 0
1 0 0
A 1 1 0

Notice that the

pull-up network is
B related to the pull-
F down network by
DeMorgan’s
Theorem!
NMOS, Pull-down PMOS, Pull-up
B A

EE40 Fall 2009 Slide 29 Prof. Cheung

 Multiple Input NOR Gate

EE40 Fall 2009 Slide 30 Prof. Cheung

 Features of CMOS Digital Circuits

• The output is always connected to VDD or GND in

steady state
 Full logic swing; large noise margins
 Logic levels are not dependent upon the relative sizes of the
devices (“ratioless”)

• There is no direct path between VDD and GND in steady

state
 no static power dissipation

EE40 Fall 2009 Slide 31 Prof. Cheung