Verilog HDL-combinational Designs

Combinational Designs

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 Verilog HDL-combinational Designs

Contents
• Part 1- 4:1 Multiplexer
• Part 2- Encoders and Decoder
• Part 3- 4-bit Ripple Carry Adder
• Part 4- Magnitude Comparator

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 Verilog HDL-combinational Designs

Part 1 Contents-4:1 Multiplexer

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 Verilog HDL-combinational Designs

4-to-1 Multiplexer
• Structural or Gate Level Design

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 Verilog HDL-combinational Designs

4-to-1 Multiplexer
//Structural or Gate Level Design
module m41(out, a, b, c, d, s0, s1);
output out;
input a, b, c, d, s0, s1;
wire sobar, s1bar, T1, T2, T3, T4;
not (s0bar, s0);
not (s1bar, s1);
and (T1, a, s0bar, s1bar);
and (T2, b, s0bar, s1);
and (T3, c, s0, s1bar);
and (T4, d, s0, s1);
or(out, T1, T2, T3, T4);
endmodule

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 Verilog HDL-combinational Designs

4-to-1 Multiplexer
// Gate Level Modeling Testbench
module mux_2_tb;
wire out;
reg a,b,c,d,s0,s1;
m41 uut(out,a,b,c,d,s0,s1);
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1, out);
$dumpvars(1, a);
$dumpvars(1, b);
$dumpvars(1, c);
$dumpvars(1, d);
$dumpvars(1, s0);
$dumpvars(1, s1);

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 Verilog HDL-combinational Designs

#5 a=0;b=1;c=0;d=1;s0=0;s1=0;
#5 $display("a=%b b=%b c=%b d=%b s0=%b s1=%b out=%b",a,b,c,d,s0,s1,out);
#5 s0=0;s1=1;
#5 $display("a=%b b=%b c=%b d=%b s0=%b s1=%b out=%b",a,b,c,d,s0,s1,out);
#5 s0=1;s1=0;
#5 $display("a=%b b=%b c=%b d=%b s0=%b s1=%b out=
%b",a,b,c,d,s0,s1,out);
#5 s0=1;s1=1;
#5 $display("a=%b b=%b c=%b d=%b s0=%b s1=%b out=
%b",a,b,c,d,s0,s1,out);
end
endmodule

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 Verilog HDL-combinational Designs

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 Verilog HDL-combinational Designs

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 Verilog HDL-combinational Designs

4-to-1 Multiplexer
out = (a. s1′.s0′) + (b.s1′.s0) + (c.s1.s0′) + (d. s1.s0)
//4X 1 multiplexer data flow modeling
module m41_df(
input a,
input b,
input c,
input d,
input [1:0]select,
output out);

assign out = ( ~select[0] & ~select[1] &a )

| ( select[0] & ~select[1] & b )
| ( ~select[0] & select[1] & c )
| ( select[0] & select[1] & d );

endmodule

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 Verilog HDL-combinational Designs

4-to-1 Multiplexer
// DATA FLOW MODELING 4:1 MULTIPLEXER TESTBENCH
module m41_df_tb;
wire out;
reg a,b,c,d;
reg [1:0] select;
m41_df uut(a,b,c,d,select,out);
initial
begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1, out);
$dumpvars(1, a);
$dumpvars(1, b);
$dumpvars(1, c);
$dumpvars(1, d);
$dumpvars(1, select);

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 Verilog HDL-combinational Designs

4-to-1 Multiplexer
#5 a=0;b=1;c=0;d=1;select=2'b00;
#5 $display("a=%b b=%b c=%b d=%b select=%b out=%b",a,b,c,d,select,out);
#5 select=2'b01;
#5 $display("a=%b b=%b c=%b d=%b select=%b out=
%b",a,b,c,d,select,out);
#5 select=2'b10;
#5 $display("a=%b b=%b c=%b d=%b select=%b out=
%b",a,b,c,d,select,out);
#5 select=2'b11;
#5 $display("a=%b b=%b c=%b d=%b select=%b out=
%b",a,b,c,d,select,out);
end
endmodule

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 Verilog HDL-combinational Designs

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 Verilog HDL-combinational Designs

4-to-1 Multiplexer

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 Verilog HDL-combinational Designs

4-to-1 Multiplexer
// conditional statement
module mux_df_cond(
input a,
input b,
input c,
input d,
input [1:0]select,
output out);

assign out = ( select == 0 )? a : ( select == 1 )? b : ( select == 2 )? c : d;

endmodule

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 Verilog HDL-combinational Designs

//conditional statement test bench

module mux_df_cond_tb;
wire out;
reg a,b,c,d;
reg [1:0] select;
mux_df_cond uut(a,b,c,d,select,out);
initial
begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1, out);
$dumpvars(1, a);
$dumpvars(1, b);
$dumpvars(1, c);
$dumpvars(1, d);
$dumpvars(1, select);

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 Verilog HDL-combinational Designs

#5 a=0;b=1;c=0;d=1;select=2'b00;
#5 $display("a=%b b=%b c=%b d=%b select=%b out=%b",a,b,c,d,select,out);
#5 select=2'b01;
#5 $display("a=%b b=%b c=%b d=%b select=%b out=%b",a,b,c,d,select,out);
#5 select=2'b10;
#5 $display("a=%b b=%b c=%b d=%b select=%b out=%b",a,b,c,d,select,out);
#5 select=2'b11;
#5 $display("a=%b b=%b c=%b d=%b select=%b out=%b",a,b,c,d,select,out);
end
endmodule

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 Verilog HDL-combinational Designs

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 Verilog HDL-combinational Designs

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 Verilog HDL-combinational Designs

4-to-1 Multiplexer

I0

I1 4-TO-
1 Y S1 S0 Y
I2 MUX 0 0 I0
I3 0 1 I1
1 0 I2
1 1 I3
S1 s0

Logic Diagram Function Table

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 Verilog HDL-combinational Designs

4-to-1 Multiplexer
//behavioral design : if else else if (sel == 2'b10)
statement
module mux4x1 (a, b, c, d, sel, out); out <= c;
input a, b, c, d; else if (sel == 2'b11)
input [1:0] sel;
out <= d;
output reg out;
always @ (a or b or c or d or sel) else
begin out<= 1'b0;
if (sel == 2'b00)
out <= a;
end
else if (sel == 2'b01) endmodule
out <= b;

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 Verilog HDL-combinational Designs

//behavioral design :if else statement test bench

module mux4X1_tb;
wire out;
reg a,b,c,d;
reg [1:0]sel;
mux4x1 uut1(a,b,c,d,sel,out);
initial
begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1, out);
$dumpvars(1, a);
$dumpvars(1, b);
$dumpvars(1, c);
$dumpvars(1, d);
$dumpvars(1, sel);

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 Verilog HDL-combinational Designs

#5 a=0;b=1;c=0;d=1;sel=2'b00;
#5 $display("a=%b b=%b c=%b d=%b sel=%b out=%b",a,b,c,d,sel,out);
#5 sel=2'b01;
#5 $display("a=%b b=%b c=%b d=%b sel=%b out=
%b",a,b,c,d,sel,out);
#5 sel=2'b10;
#5 $display("a=%b b=%b c=%b d=%b sel=%b out=
%b",a,b,c,d,sel,out);
#5 sel=2'b11;
#5 $display("a=%b b=%b c=%b d=%b sel=%b out=%b",a,b,c,d,sel,out);
end
endmodule

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 Verilog HDL-combinational Designs

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 Verilog HDL-combinational Designs

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 Verilog HDL-combinational Designs

//behavioral design : case statement

// behavioral case statement
module mux_4_case(a,b,c,d,sel,out);
input a,b,c,d;
input [1:0] sel;
output reg out;

always @(*)
case (sel)
2'b00 : out<= a;
2'b01 : out<= b;
2'b10 : out <= c;
default : out <= d;
endcase
endmodule

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 Verilog HDL-combinational Designs

// behavioral case statement test bench

module mux_4_case_tb;
wire out;
reg a,b,c,d;
reg [1:0]sel;
mux_4_case uut1(a,b,c,d,sel,out);
initial
begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1, out);
$dumpvars(1, a);
$dumpvars(1, b);
$dumpvars(1, c);
$dumpvars(1, d);
$dumpvars(1, sel);

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 Verilog HDL-combinational Designs

#5 a=0;b=1;c=0;d=1;sel=2'b00;
#5 $display("a=%b b=%b c=%b d=%b sel=%b out=%b",a,b,c,d,sel,out);
#5 sel=2'b01;
#5 $display("a=%b b=%b c=%b d=%b sel=%b out=%b",a,b,c,d,sel,out);
#5 sel=2'b10;
#5 $display("a=%b b=%b c=%b d=%b sel=%b out=%b",a,b,c,d,sel,out);
#5 sel=2'b11;
#5 $display("a=%b b=%b c=%b d=%b sel=%b out=%b",a,b,c,d,sel,out);
// #5 sel=2'b11;
// $display("a=%b b=%b c=%b d=%b sel=%b out=%b",a,b,c,d,sel,out);
end
endmodule

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 Verilog HDL-combinational Designs

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 Verilog HDL-combinational Designs

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 Verilog HDL-combinational Designs

Part 2 Encoders and Decoders

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 Verilog HDL-combinational Designs

Encoders (2:4)

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 Verilog HDL-combinational Designs

2:4 Encoder (Behavioral Modeling)

module encoder_2_4(
input [3:0] in,
output reg[1:0] y
);
always @(in) begin
if (in == 4'b0001) y = 0; else
if (in == 4'b0010) y = 1; else
if (in == 4'b0100) y = 2; else
if (in == 4'b1000) y = 3; else
y = 2'bx;
end

endmodule

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 Verilog HDL-combinational Designs

Test bench
module encoder_2_4_tb;

// Inputs
reg [3:0] in;

// Outputs
wire [1:0] y;

// Instantiate the Unit Under Test (UUT)

encoder_2_4 uut (
.in(in),
.y(y)
);

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 Verilog HDL-combinational Designs

initial begin

// Initialize Inputs
$dumpfile("dump.vcd");
$dumpvars(1, in);
$dumpvars(1, y);
$monitor( "in=%b, y=%b",in, y);

// Wait 100 ns for global reset to finish

in = 4'b0001;
#3 in = 4'b0010;
#4 in = 4'b0100;
#5 in = 4'b1000;
end

endmodule

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 Verilog HDL-combinational Designs

Decoder (2:4 with active low enable)

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 Verilog HDL-combinational Designs

2:4 Decoder (Gate Level)

// Gate-level description of 2-to-4 decoder
module decoder( D, A, B, enable );
output [0:3] D; // vector of 4 bits
input A, B;
input enable;
wire Anot, Bnot, enableNot;
not
G1 (Anot, A), // note syntax: list of gates
G2 (Bnot, B), // separated by ,
G3 (enableNot, enable);
nand
G4 (D[0], Anot, Bnot, enableNot ),
G5 (D[1], Anot, B, enableNot ),
G6 (D[2], A, Bnot, enableNot ),
G7 (D[3], A, B, enableNot );
endmodule

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 Verilog HDL-combinational Designs

Test bench
module decoder_tb;
reg A;
reg B;
reg enable;
wire [0:3] D;
decoder uut (
.D(D),
.A(A),
.B(B),
.enable(enable)
);

initial begin
$dumpfile("dump.vcd");
$dumpvars(1, enable);
$dumpvars(1, A);
$dumpvars(1, B);
$dumpvars(1, D);

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 Verilog HDL-combinational Designs

$monitor($time, ": enable=%b, A=%b, B=%b, D=%b", enable, A, B, D);

A = 0;
B = 0;
enable = 1;
enable = 0;
// Wait 100 ns for global reset to finish
#100 A = 0;
#100 B = 0;
#100 A = 0;
#100 B = 1;
#100 A = 1;
#100 B = 0;
#100 A = 1;
#100 B = 1;
// Add stimulus here

end

endmodule

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 Verilog HDL-combinational Designs

2:4 Decoder (behavioral)

module decoder_beh(input [1:0] x,input enable_n, output reg[3:0] y);
// a 2-to-4 decoder with active low output
always @(x or enable_n)
if (enable_n) y = 4'b1111; else
case (x)
2'b00 : y = 4'b1110;
2'b01 : y = 4'b1101;
2'b10 : y = 4'b1011;
2'b11 : y = 4'b0111;
endcase

endmodule

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 Verilog HDL-combinational Designs

Test bench
module decoder_beh_tb;

// Inputs
reg [1:0] x;
reg enable_n;

// Outputs
wire [3:0] y;

// Instantiate the Unit Under Test (UUT)

decoder_beh uut (
.x(x),
.enable_n(enable_n),
.y(y)
);

initial begin
$monitor( ": enable_n=%b, x=%b, y=%b", enable_n, x, y);

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 Verilog HDL-combinational Designs

// Initialize Inputs
$dumpfile("dump.vcd");
$dumpvars(1, enable_n);
$dumpvars(1, x);
$dumpvars(1, y);
enable_n = 1;
enable_n = 0;
// Wait 100 ns for global reset to finish
x = 2'b00;
#2 x = 2'b01;
#2 x = 2'b10;
#2 x = 2'b11;
end

endmodule

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 Verilog HDL-combinational Designs

2:4 Decoder (Data flow)

module decoder_2x4_df(
output [0: 3] D,
input A, B,enable
);
assign D[0] = !((!A) && (!B) && (!enable));
assign D[1] = !(!A) && B && (!enable);
assign D[2] =!(A && B && (!enable));
assign D[3] = !(A && B && (!enable));
endmodule
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 Verilog HDL-combinational Designs

module decoder_2x4_df_tb;

// Inputs
reg A;
reg B;
reg enable;

// Outputs
wire [0:3] D;

// Instantiate the Unit Under Test (UUT)

decoder_2x4_df uut (
.D(D),
.A(A),
.B(B),
.enable(enable)
);

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 Verilog HDL-combinational Designs

initial begin
$monitor( ": enable=%b, A=%b, B=%b D=%b", enable, A, B,D);
$dumpfile("dump.vcd");
$dumpvars(1, enable);
$dumpvars(1, A);
$dumpvars(1, B);
$dumpvars(1, D);
// Initialize Inputs
enable = 1;
A = 0;
B = 0;
# 5 enable = 0;

// Wait 100 ns for global reset to finish

#10 A = 0;
#10 B = 1;

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 Verilog HDL-combinational Designs

#10 A = 1;
#10 B = 0;

#10 A = 1;
#10 B = 1;
// Add stimulus here

end

endmodule

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 Verilog HDL-combinational Designs

Part3: 4-bit Ripple Carry Adder

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 Verilog HDL-combinational Designs

Half adder

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 Verilog HDL-combinational Designs

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 Verilog HDL-combinational Designs

// Description of half adder

module halfadder (S, C, x, y);
input x, y;
output S, C;
// Instantiate primitive gates
xor (S, x, y);
and (C, x, y);
endmodule
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 Verilog HDL-combinational Designs

// Description of full adder

module fulladder (S, C, x, y, z);
input x,y,z;
output S,C;
wire S1,D1,D2; //Outputs of first XOR and two AND gates
//Instantiate the halfadders
halfadder HA1 (S1,D1,x, y);
halfadder HA2 (S, D2,S1,z);
or g1(C,D2,D1);
endmodule
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 Verilog HDL-combinational Designs

// Description of 4-bit adder (see Fig 4-9)

module Four_bit_adder (S,C4,A,B,C0);
input [3:0] A,B;
input C0;
output [3:0] S;
output C4;
wire C1,C2,C3; //Intermediate carries
// Instantiate the fulladder
fulladder FA0 (S[0],C1,A[0],B[0],C0);
fulladder FA1 (S[1],C2,A[1],B[1],C1);
fulladder FA2 (S[2],C3,A[2],B[2],C2);
fulladder FA3 (S[3],C4,A[3],B[3],C3);
endmodule

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 Verilog HDL-combinational Designs

module testAdder;
reg [3:0] A;
reg [3:0] B;
reg carryIn;
wire [3:0] Sum;
wire carryOut;
Four_bit_adder adder( Sum, carryOut, A, B, carryIn );
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1, A);
$dumpvars(1,B);
$dumpvars(1, carryIn);
$dumpvars(1, Sum);
$dumpvars(1, carryOut);

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 Verilog HDL-combinational Designs

A = 4'b1001; B = 4'b1011; carryIn = 1'b0;

#10
$display( " %b", A );
$display( " %b", B );
$display( "%b %b", carryOut, Sum );
end
initial
#20 $finish;
endmodule
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 Verilog HDL-combinational Designs

Part 4:Magnitude Comparator

module mag_compare ( output A_lt_B, A_eq_B,
A_gt_B,input [3: 0] A, B);
assign A_lt_B =(A < B);
assign A_gt_B =(A > B);
assign A_eq_B = (A == B);
endmodule

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 Verilog HDL-combinational Designs

module mag_compare_tb;

// Inputs
reg [3:0] A;
reg [3:0] B;

// Outputs
wire A_lt_B;
wire A_eq_B;
wire A_gt_B;

// Instantiate the Unit Under Test (UUT)

mag_compare uut (
.A_lt_B(A_lt_B),
.A_eq_B(A_eq_B),
.A_gt_B(A_gt_B),
.A(A),
.B(B)
);

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 Verilog HDL-combinational Designs

initial begin
$monitor( ": A=%b, B=%b A_lt_B=%b A_eq_B=%b A_gt_B=%b", A,B,A_lt_B,A_eq_B,A_gt_B);
$dumpfile("dump.vcd");
$dumpvars(1, A);
$dumpvars(1, B);
$dumpvars(1, A_lt_B);
$dumpvars(1, A_eq_B);
$dumpvars(1, A_gt_B);
// Initialize Inputs
// Initialize Inputs
A = 4'b0000;
B = 4'b0000;
#100 A = 4'b0001;
#100 B = 4'b0000;
#100 A = 4'b0000;
#100 B = 4'b0001;
end
endmodule

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