Mixed Signal Circuit Design ELL 731

Download as pptx, pdf, or txt
Download as pptx, pdf, or txt
You are on page 1of 11

Mixed Signal Circuit Design

ELL 731

Prof Rakesh Kumar Palani


Department of Electrical Engineering
Indian Institute of Technology, Delhi
Hauz Khas, New Delhi 110016
Why Analog is interesting?
• Analog design is art and science at the same time.
• Art  It requires creativity to strike the right
compromises between the specifications imposed
• Science  It requires a certain level of methodology
to carry out a design
-- Wiley Sansen

slide 2
Why Analog is interesting?
• There is not one solution to a problem
– Each one can arrive at same solution via different routes
– It depends on the creativity of individuals

slide 3
Why do we need Analog?
• World is analog, unless you look at quantum
levels
• All signals by nature is analog
– Some signal conditioning is done in analog before A-
D
– All processing in done in digital
– Signal transmitted back to world in analog
An example

DSP
ADC DAC
Memory

slide 4
ELL 731 Course Structure
• Class Timing A slot, M/Th 8-9:30 am
• Instructor : Prof Rakesh Palani
• TA – Nikhil Kumar Singh (eey207618@ee.iitd.ac.in)
• No Text book
– Class Lecture notes.
• Please use Piazza/email for discussion
– piazza.com/iitd.ac.in/spring2022/ell731
– Reference:
– Behzad Razavi, Principles of Data Conversion System Design

slide 5
ELL 731 Course Structure
• Teaching presently is online
• Live classes through MS Teams
• Attendance is 60 %
• Failing short will lead to F grade of NF.

slide 6
ELL 731 Grading
• Minor : 20 points Points Grade
• Major : 30 points 80- A
100
• Project : 35 points
70-80 A-
• Assignment : 10 point 60-70 B
• Active Participation * : 5 point 50-60 B-
• Absolute Grading 40-50 C
• All points will be rounded to the nearest integer 35-40 C-

– Eg 79.5 gets rounded 80 and he/she gets A 30-35 D


20-30 E
– 79.4 gets rounded to 79 and he/she gets A-
0-20 F

• *Active participation grade will be dependent on instructor

slide 7
Project
• Major Learning is done through project
• Project has lot of weightage.
• Form a Team of 2 or 3
– Design ideal model of ADC (cadence or matlab)
– Incorporate non-idealities
– Study its effect on ADC performance
– Corelate with theory in class

• Each Individual
– Design a Sch of comparator/sampler/Digital Logic

slide 8
ELL 731 Project
Project Deadline Grade Deliverable
Project Topic Feb 1 2022 5 ADC Architecture Selection, Team
Selection Members, Specifications
Initial March 1 20 Ideal Model Sims, Study of impact
2022 of nonidealities on the architecture
Final Report March 26 10 Schematic sim
2022

• Final Report
• All schematics should be done across corners, FF,SS,TT, -40,125
• No extension of the deadlines whatsoever may be reason
– Please don’t ask for it

slide 9
ELL 731 Honor Code
• Cheating in any form will incur serious penalities
– Remember grading is absolute
– Found in any project or exams will result in 0 point
– Remaining portion of the grade will be scaled by 50%
• For eg found cheating once in tutorial 1
– Your score = 0 in tut1 +0.5(score of remaining tutorials)
– Report to DISCO, IIT Delhi
– Second time cheating in tutorial say 5
– Your score = 0 in tut1+ 0 in tut5 + 0.25(score of remaining tutorials)
• We will trust you and we will try not to tempt you
• Try not to place us in this unpleasant situation

slide 10
Syllabus
• Sampling
• Quantization
• Spectral Performance Metrics
• Samplers
• Comparators
• Flash/SAR/Pipelined ADC
• Oversampled converters
• Current Steering and Resistive DACs

slide 11

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy