SRI RAMAKRISHNA INSTITUTE OF TECHNOLOGY, COIMBATORE-10

(An Autonomous Institution)

(Approved by AICTE, New Delhi and permanently Affiliated to Anna University, Chennai)

FLIP-FLOPS, TRIGGERING, MASTER SLAVE

CONFIGURATION

Ms.R.Gayathri,
Assistant Professor (Sr. Gr.)/ECE
Two Types of Switching Circuits
• Combinational Circuits
– Combinational circuits have only input and output. Output
depends on input.
– Example: AND,OR,NAND,NOR,XOR etc

• Sequential Circuits
– Sequential circuits have input, present state, next state and
output. Next state depends upon present state and input.
Output depends upon present state and input
– Example: Flip-Flops etc
 Sequential Digital Circuits
• Sequential circuits are digital circuits in which the outputs
depend not only on the current inputs, but also on the
previous state of the output.
• They basic sequential circuit elements can be divided in two
categories:
• Level-sensitive (Latches)
o High-level sensitive
o Low-level sensitive
• Edge-triggered (Flip-flops)
o Rising (positive) edge triggered
o Falling (negative) edge triggered
o Dual-edge triggered

4
Clocked Sequential Circuits

5
 Synchronous vs. Asynchronous
• The behavior of a synchronous sequential circuit
depends upon the any input signal at any instant of
time and order of input change. This synchronization
is achieved by clock generators that provides clock
pulses (see the next slide). The storage elements used
in clocked sequential circuits are called flip-flops.

• In asynchronous sequential circuits the storage

elements are time delay devices (i.e., storage is
because of their propagation delay). They
implemented by feedback that may cause instability
in Asynchronous circuits.

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 Edge-Triggered vs. Level sensitive
• ET FF: Transition (output change) can happen only
during clock pulse transition
• Clock pulse transition can be positive clock transition
or negative clock transition
• Level Sensitive FF: as long as the pulse level is up or
down output can change
• Level sensitive clock is less favorite because
depending on the duration of pulse, output may
change a number of times

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Clock Responses in Latches and Flip flops

8
 The Set/Reset (SR) Latch
The Set/Reset latch is the most basic unit of sequential digital circuits. It has two
inputs (S and R) and two outputs outputs Q and Q’. The two outputs must always be
complementary, i.e if Q is 0 then Q’ must be 1, and vice-versa. The S input sets the
Q output to a logic 1. The R input resets the Q output to a logic 0.

Circuit Diagram Truth Table

R
Q S R Q+ Q΄+ Function

0 0 Q Q΄ Latch
0 1 0 1 Reset
1 0 1 0 Set
Q
S 1 1 0 0 Illegal

S
Q Logic Symbol

S Q

R Q
Q
R

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 The Gated Set/Reset (SR) Latch
To be able to control when the S and R inputs of the SR latch can be applied to the
latch and thus change the outputs, an extra input is used. This input is called the
Enable. If the Enable is 0 then the S and R inputs have no effect on the outputs of the
SR latch. If the Enable is 1 then the Gated SR latch behaves as a normal SR latch.

Circuit Diagram Truth Table Truth Table

S EN S R Q+ EN S R Q+ Function
S Q Q
0 0 0 Q 0 X X
EN

R Q Q 0 0 1 Q 1 0 0
R
0 1 0 Q 1 0 1
0 1 1 Q 1 1 0
Logic Symbol
1 0 0 Q 1 1 1

S Q 1 0 1 0
EN 1 1 0 1
R Q
1 1 1 U

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 The Data (D) Latch
A problem with the SR latch is that the S and R inputs can not be at logic 1 at
the same time. To ensure that this can not happen, the S and R inputs can by
connected through an inverter. In this case the Q output is always the same as
the input, and the latch is called the Data or D latch. The D latch is used in
Registers and memory devices.

Circuit Diagram Truth Table Truth Table

D EN D Q Q+ EN D Q+ Function
S Q Q
0 0 0 Q 0 0
EN
0 0 1 Q 0 1
R Q Q
0 1 0 Q 1 0
0 1 1 Q 1 1
Logic Symbol
1 0 0 0
D Q
1 0 1 0
EN
1 1 0 1
Q
1 1 1 1

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 The JK Latch
Another way to ensure that the S and R inputs can not be at logic 1 simultaneously, is
to cross connect the Q and Q’ outputs with the S and R inputs through AND gates.
The latch obtained is called the JK latch. In the J and K inputs are both 1 then the Q
output will change state (Toggle) for as long as the Enable 1, thus the output will be
unstable. This problem is avoided by ensuring that the Enable is at logic 1 only for a
very short time, using edge detection circuits.

Circuit Diagram Truth Table Truth Table

EN J K Q Q+ EN J K Q+ Function
J S Q Q
0 X X X Q 0 X X
EN
1 0 0 0 0 1 0 0
K R Q Q
1 0 0 1 1 1 0 1
1 0 1 0 0 1 1 0
Logic Symbol
1 0 1 1 0 1 1 1
J Q 1
1 1 0 0
EN
1 1 0 1 1
K Q
1 1 1 0 1
1 1 1 1 0

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 Edge Detection Circuits
Edge detection circuits are used to detect the transition of the Enable from logic 0 to
logic 1 (positive edge) or from logic 1 to logic 0 (negative edge). The operation of
the edge detection circuits shown below is based on the fact that there is a time delay
between the change of the input of a gate and the change at the output. This delay is
in the order of a few nanoseconds. The Enable in this case is called the Clock (CLK)

Positive Edge Detection Negative Edge Detection

EN
EN' EN
EN'
EN
EN
EN

EN EN

EN

EN
EN

EN' EN'

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 The JK Edge Triggered Flip Flop

The JK edge triggered flip flop can be obtained by inserting an edge detection circuit
at the Enable (CLK) input of a JK latch. This ensures that the outputs of the flip flop
will change only when the CLK changes (0 to 1 for +ve edge or 1 to 0 for –ve edge)

Positive Edge JK Flip Flop Negative Edge JK Flip Flop

J J
S Q Q S Q Q

CLK CLK

R Q Q R Q Q
K K

CLK J K QN+1 Function CLK J K QN+1 Function

Logic Symbol Logic Symbol
X X Q X X
J Q J Q
0 0 Q 0 0
CLK CLK
K Q 0 1 0 K Q 0 1
1 0 1 1 0
1 1 Q’ 1 1

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 The D Edge Triggered Flip Flop
The D edge triggered flip flop can be obtained by connecting the J with the K
inputs of a JK flip through an inverter as shown below. The D edge trigger can
also be obtained by connecting the S with the R inputs of a SR edge triggered
flip flop through an inverter.

Positive Edge D Flip Flop Negative Edge D Flip Flop

D J Q Q D J Q Q

CLK CLK

K Q Q K Q Q

Logic Symbol CLK D QN+1 Function Logic Symbol CLK D QN+1 Function
D Q X Q D Q X Q
CLK 0 CLK 0
0 0
Q Q 1
1 1 1

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 The Toggle (T) Edge Triggered Flip Flop
The T edge triggered flip flop can be obtained by connecting the J with the K
inputs of a JK flip directly. When T is zero then both J and K are zero and the
Q output does not change. When T is one then both J and K are one and the Q
output will change to the opposite state, or toggle.

Positive Edge T Flip Flop Negative Edge T Flip Flop

T J Q Q T J Q Q

CLK CLK

K Q Q K Q Q

Logic Symbol CLK T QN+1 Function Logic Symbol CLK T QN+1 Function
T Q X Q T Q X Q
CLK 0 Q CLK 0 Q
Q 1 Q΄ Q 1 Q΄

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 The JK Master Slave Flip Flop

• All sequential circuits have a problem (All level sensitive sequential

circuits have this problem). Before the enable input changes state from
HIGH to LOW (assuming HIGH is ON and LOW is OFF state), if inputs
changes, then another state transition occurs for the same enable pulse.
This sort of multiple transition problem is called racing.
• If we make the sequential element sensitive to edges, instead of levels, we
can overcome this problem, as input is evaluated only during enable/clock
edges.
Thank you