L9,10 Flip Flops

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Basic Sequential Components

Flip-Flop (FF)
• Flip-Flop is a memory element used in sequential
circuit
• FF is an electronic device which has two stable
states hence it is a bi-stable device.
• FF has two outputs, one is 0 and other is +5 Vdc
• When the FF has its o/p set at 0 Vdc, it can be
regarded as storing a logic 0 and when its o/p is set
at +5 Vdc it stores logic 1
• FF is capable of serving as one bit of memory
Clock-A Timing Signal
• It is usually derived from an oscillator or other
circuitry that alternates its output between 1 and 0
• It is used to synchronize the flow of data in a
digital system
1
0
Rising (positive)
Edge
Falling (negative)
Edge
Positive Level

Negative Level
Level Triggered

• A FF is said to be level triggered if data present at I/P are


transferred to O/P only when clock signal reaches its peak
or lowest
• Positive level triggered: data transfer takes place when
clock signal reaches its peak value
• Negative level triggered: data transfer takes place when
clock signal reaches its lowest value
Edge Triggered
• A FF is said to be edge triggered if data present at I/P are
transferred to O/P only at transition in the clock signal
• Positive edge triggered: data transfer takes place at 0-to-1
transition
• Negative edge triggered: data transfer takes place at 1-to-
0 transition

State
State represents what is stored in memory.
Previous State:State of FF before the occurrence of a CLK
Next State :State of FF after the occurrence of a CLK
SR latch
• The most fundamental
latch is the simple SR
latch, where S and R
stand for set and reset.
• It can be constructed
from a pair of cross- Logic
coupled NOR (negative Diagram
OR) logic gates.
• It is called NOR-Gate S R Qn+1 Q’n+1
Latch 0 0 NC(Qn) NC(Q’n)
• The stored bit is present Reset
0 1 0 1
on the output marked Q  Set
1 0 1 0
1 1 RACE RACE
• When both S and R are 0, the output remains unchanged
i.e. here next state=previous state
• When S=1, R=0, irrespective of previous condition latch is
set to ‘SET’ state
• Similarly when S=0, R=1,it resets the latch to 0
• when both the S and R are 1, the output of the latch is
undefined; here both the outputs will try to reach 0, in other
words Q=0 and Q’=0 at the same time! which violets the
basic definition of FF that requires Q to be complement of
Q’, it leads to RACE condition of the circuit
• the designer has to ensure that S and R inputs are never set
to 1, if this condition is imposed then the result state is
unpredictable
• Doesn’t have a clock input
SR Latch Using NAND gates :

•It is also called NAND-


GATE Latch
•The truth table for NAND-
gate latch is different from
that for NOR-gate latch
S R Qn+1 Q’n+1
0 0 RACE RACE
Reset
0 1 0 1
1 0 1 0  Set
1 1 NC(Qn) NC(Q’n)
Clocked SR Flip-Flop
Inputs Outputs

CLK S R Qn+1 Q’n+1

0 X X Qn Q’n
1 0 0 Qn Q’n
1 0 1 0 1
1 1 0 1 0
1 1 1 RACE RACE

• When CLK level=0 irrespective of S and R inputs, Output


remains the same
• When CLK=1, S=0, R=0 Output will not change
• When CLK=1, S=1, R=0 Output is in SET state
• When CLK=1, S=0, R=1 Output is in RESET state
• When CLK=1, S=1, R=1 RACE condition
Assignment1:
Implement cloked SR FF using NAND gates and derive the
corresponding Truth table.

Solution:
Preset and Clear
Preset(Pr)
• When power supply is switched on,
the state of circuit is uncertain.
Output is set or reset, i.e. S Q
unpredictable. CLK SR FF

• In some applications user want Q to R Q’


be very specific either SET or
RESET. Clear(Cr)
• Hence we have to consider initial
condition. To accomplish initial
condition we use Preset (direct set)
and clear (direct reset) terminal.
• These inputs can be given in 2 ways:
1) Synchronism with CLK
(Synchronous Preset/Clear)
2) Asynchronism with CLK
(Asynchronous Preset/Clear)
SR FF with Preset and Clear

Inputs Outputs
Pr Cr CLK S R Qn+1 Q’n+1
X X 0 X X Qn Q’n
0 0 1 X X RACE RACE
0 1 1 X X 0 1
1 0 1 X X 1 1
1 1 1 0 0 Qn Q’n
1 1 1 0 1 0 1
1 1 1 1 0 1 0
1 1 1 1 1 RACE RACE
Truth table of Synchronous Preset and Clear
Inputs Outputs
Pr Cr CLK S R Qn+1 Q’n+1
0 0 X X X RACE RACE
0 1 X X X 1 0
1 0 X X X 0 1
1 1 0 X X Qn Q’n
1 1 1 0 0 Qn Q’n
1 1 1 0 1 0 1
1 1 1 1 0 1 0
1 1 1 1 1 RACE RACE

Truth table of Asynchronous Preset and Clear


Unclocked D FF
• To avoid possibility of race condition in SR FF , D flip flop
is designed
• An SR FF is converted to a D FF by inserting an inverter
between S and R and assigning the symbol D to the single
input.
• Note here that output Q changes as D changes, irrespective
of previous state.
• Here Qn+1 is simply copy of D input, So functionally D FF
produces o/p which is equal to input but with some ‘Delay’.
So it is called as delay FF.

D Input Qn+1 Q’n+1


0 0 1
1 1 0
Clocked D FF
Logic Diagram :

Level triggered D FF
• Below is truth table of Positive level triggered D FF
• When CLK level=0 irrespective of D input, Output remains
the same
• When CLK=1 output Q changes as D changes

Input Output
CLK D Qn+1 Q’n+1
Truth table of positive Level 0 X Qn Q’n
triggered D FF 1 0 0 1
1 1 1 0
Edge triggered D FF
• Below is truth table of Positive edge triggered D FF
• When CLK =0 or CLK=1 irrespective of D input, Output
remains the same
• When CLK= ↓ i.e. when CLK signal performs 1-to-0
transition, irrespective of D input, Output remains the same
• When CLK= ↑ i.e. when CLK signal performs 0-to-1
transition, output Q changes as D changes

Input Output
CLK D Qn+1 Q’n+1
0 X Qn Q’n
1 X Qn Q’n
↓ X Qn Q’n
↑ 0
0 1
↑ 1
Graphical symbol of 1 0
Truth table of positive edge triggered D FF
edge triggered D FF
JK flip-flop

Graphical symbol

Logic diagram

• Resolves the problem of undefined outputs associated with


SR latch
• It is often used instead of SR latch.
Inputs Outputs
Truth table of positive edge CLK J K Qn+1 Q’n+1
triggered JK FF 0 X X Qn Q’n
1 X X Qn Q’n
↓ X X Qn Q’n
↑ 0 0
Qn Q’n
↑ 0 1
↑ 1 0 0 1
↑ 1 1 1 0
Q’n Qn
• When CLK is at HIGH or LOW level, both O/Ps remains in
previous state
• When CLK performs transition from 1-to-0, both O/Ps remains
in previous state
• When CLK performs transition from 0-to-1, I/P determines the
O/P :
 when J=0, K=0 then state remains unchanged
 when J=0, K=1 then O/P is in Reset state
 when J=1, K=0 then O/P is in Set state
 when J=0, K=1 then O/P is in Toggle state i.e. if Q=1, it
switches to Q=0 and vice versa
T (toggle) flip-flop

• T FF has only one input T


• The T input doesn’t specify a value for its output, it specifies
only whether or not the output should be changed
• T FF changes its state every clock cycle if its input T is equal
to 1
Input Output
Truth table of positive edge CLK T Qn+1 Q’n+1
triggered T FF 0 X Qn Q’n
1 X Qn Q’n
↓ X Qn Q’n
↑ 0
Qn Q’n
↑ 1
Q’n Qn

• When CLK is at HIGH or LOW level, both O/Ps remains in


previous state
• When CLK performs transition from 1-to-0, both O/Ps remains
in previous state
• On the rising edge of the clock, if T = 0 then the output of the
flip-flop is unchanged; if T=1, the output is inverted i.e. O/P is in
Toggle state
Master Slave JK FF

Slave
Master
• A master-slave flip-flop is constructed from two seperate flip-
flops. One circuit serves as a master and the other as a slave.
• Master is positive edge triggered and slave is negative edge
triggered, so when master is active, slave is inactive and vice
versa.
• Master responds to its J & K inputs before the slave
• If J=1, K=0 master sets on positive clock transition. The high
o/p of the master drives the J i/p of the slave, so on the negative
clock transition, the slave sets.
• If J=0, K=1, master resets on the PT of clock. The high Q’
output of master goes to the K input of slave. So the NT of
clock forces the slave to reset. Again slave has copied the
master.
• If J=1, K=1, master toggles on the PT of the clock and the slave
then toggles on the clock NT. Regardless of what the master
does, slave copies it.
• If J=K=0, the FF is disabled and Q remains unchanged.
Observations
• Most commonly used flip-flops are D FFs because
they are useful for temporary storage of data
• Counter circuits can be implemented efficiently by
using T FFs
• JK FF combines the behaviours of SR and T FFs
• The JK FF is versatile. It can be used to store data
just as D FF. It can also be used to build counters, as
it behaves like T FF if J and K input terminals are
connected together.
• All of the flip-flops and latches shown so far are
positive edge triggered or positive level triggered.
They also have active high load, set and clear
inputs.
• It is possible for those components to be negative
edge triggered or negative level triggered and have
active low control signals as well.
• Flips-flops and latches can be combined in parallel
to store data with more than one bit

Applications:
Counter/Timer, register
Memory element, eliminating keyboard debouncing etc

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