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    8255 New

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    mohit mishra
    The document discusses the 8255 Programmable Peripheral Interface (PPI) chip. It covers the basics of the 8255 PPI, including its 3 programmable 8-bit I/O ports that allow a microprocessor to communicate with external devices. It describes the pin details and internal block diagram of the 8255. It also explains the different modes of operation for the 8255 ports, including bit set/reset mode and I/O modes 0, 1, and 2, and provides the control word formats for programming these modes.

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    8255 New

    Uploaded by

    mohit mishra
    27 views13 pages
    The document discusses the 8255 Programmable Peripheral Interface (PPI) chip. It covers the basics of the 8255 PPI, including its 3 programmable 8-bit I/O ports that allow a microprocessor to communicate with external devices. It describes the pin details and internal block diagram of the 8255. It also explains the different modes of operation for the 8255 ports, including bit set/reset mode and I/O modes 0, 1, and 2, and provides the control word formats for programming these modes.

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    8255 NEW

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    The document discusses the 8255 Programmable Peripheral Interface (PPI) chip. It covers the basics of the 8255 PPI, including its 3 programmable 8-bit I/O ports that allow a microprocessor to communicate with external devices. It describes the pin details and internal block diagram of the 8255. It also explains the different modes of operation for the 8255 ports, including bit set/reset mode and I/O modes 0, 1, and 2, and provides the control word formats for programming these modes.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    27 views13 pages

    8255 New

    Uploaded by

    mohit mishra
    The document discusses the 8255 Programmable Peripheral Interface (PPI) chip. It covers the basics of the 8255 PPI, including its 3 programmable 8-bit I/O ports that allow a microprocessor to communicate with external devices. It describes the pin details and internal block diagram of the 8255. It also explains the different modes of operation for the 8255 ports, including bit set/reset mode and I/O modes 0, 1, and 2, and provides the control word formats for programming these modes.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 13

    8255 Programmable Peripheral

    Interface
    (UNIT-4)

    (SUB: Microprocessor and Interfaces)

    PREPARED BY:
    ER. MOHIT MISHRA
    ASSOCIATE PROFESSOR
    COMPUTER SCIENCE DEPARTMENT
    TOPIC COVERED
    • The BASICS OF 8255 PPI
    • PIN DETAILS
    • INTERNAL BLOCK DIAGRAM OF 8255
    • BLOCK DIAGRAM FEATURES
    • DIFFERENT MODES OF 8255
    • CONTROL WORD FORMAT FOR BIT SET RESET MODE
    • CONTROL WORD FORMAT FOR I/O MODE
    The BASICS OF 8255 PPI
    PPI = Programmable Peripheral Interface
    • The 8255 allows the microprocessor to communicate
    with the outside world through three programmable 8-
    bit wide I/O ports
    • The PC uses a few 8255 (in the chip set) to control the
    keyboard, speaker, and parallel port
    • The 8255 PPI is available in DIP or surface mount
    forms
    • Also implemented as functions within modern interface
    chip sets
    PIN DETAILS
    INTERNAL BLOCK DIAGRAM OF 8255
    BLOCK DIAGRAM FEATURES
    Data bus buffer:
    ●This is a tri state bidirectional buffer used to interface the 8255 to system

    data bus. Data is transmitted or received by the buffer on execution of input


    or output instruction by the CPU.

    • Control word and status information are also transferred


    through this unit.
    READ/WRITE CONTROL LOGIC
    This unit accepts control signals ( RD, WR ) and also inputs from address bus and
    issues commands to individual group of control blocks
    ( Group A, Group B).It has the following pins.
    a) CS – Chipselect : A low on this PIN enables the
    communication between CPU and 8255.
    b) RD (Read) – A low on this pin enables the CPU to read
    the data in the ports or the status word through data bus buffer.
    c) WR ( Write ) : A low on this pin, the CPU can write
    data on to the ports or on to the control register through
    the data bus buffer.
    d) RESET: A high on this pin clears the control register
    and all ports are set to the input mode
    e) A0 and A1 ( Address pins ): These pins in conjunction
    with RD and WR pins control the selection of one of the
    3 ports.
    I/O PORT ASSIGNMENTS
    • Group A is Port A and A1 A0 Function
    upper ½ of Port C
    (PC7-PC4).
    • Group B is Port B and 0 0 Port A
    lower ½ of Port C (PC3-
    PC0). 0 1 Port B

    1 0 Port C
    Writing into this register
    programs the various ports to operate in
    various modes and be used 1 1 Command Register
    as either inputs or outputs
    I/O PORT ADDRESS

    Data bus
    D[7:0]
    PA[7:0]
    A0
    8085 A1 PB[7:0]
    RD Control port
    WR PC[7:0]
    RESET
    A7 CS
    A6
    A5 A1 A0 Port
    A4
    A3 0 0 PA
    A2 0 1 PB
    IO/M 1 0 PC
    1 1 Control
    DIFFERENT MODES OF 8255

    8255 has two different modes:


    • Bit Set – Reset mode
    • I/O modes

    • I/O mode further divided into three modes


    • MODE 0
    • MODE 1
    • MODE 2
    CONTROL WORD FORMAT FOR BIT SET RESET
    MODE
    CONTROL WORD FORMAT FOR I/O MODE
    I/O MODE
    Mode 0: Simple Input or Output
    • Ports A, B, and C can be individually programmed as
    input or output ports
    • Port C is divided into two 4-bit ports which are
    independent from each other
    Mode 1: Input /Output Control Signals
    • Ports A and B are programmed as input or output ports
    • Port C is used for handshaking
    Mode 2: Bidirectional Data transfer
    • Port A is programmed to be bi-directional
    • Port C is for handshaking
    • Port B can be either input or output in mode 0 or mode 1

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