2 Pins and Signals of 8085

 Statistical Analysis of Chapter 2


Year 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20
IES(obj) 2 1 1 1 1
E&T IES(Con) 8 12
GATE
IES(obj) 2 1 1 1 1 2 1 1 2 2
IES(Con) 4 12
EE
GATE
IAS(mains) 20 5 4 10 10
IN GATE 2 1 1
* Number in box is no. of Questions for IES (obj) and marks for all other exams

Conclusion
This chapter has frequent questions in IES objective paper of Electronics and
Telecommunication Engineering as well as in Electrical Engineering. So, this
chapter can be studied from objective point of view for IES examination. This
chapter is also essential for understanding of microprocessor 8085.

2.1 Introduction
Microprocessor 8085 is a 40 pin 8 bit general purpose microprocessor which operates at 3
MHz - 5MHz. The word size of 8085 is 8 bits. By using the 8 bits 256 different Op codes can
be formed but practically only 246 has been used. There are 74 different mnemonics used
for 246 instructions of 8085.

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Pins and Signals of 8085 [2]

2.2 Pins Configuration

X1 1 40 VCC
X2 2 39 HOLD
RESET OUT 3 HLDA
38
SOD 4 CLK (OUT)
SID 5 37 RESET IN
TRAP 6 36 READY
RST 7.5 7 34 IO/M
35
RST 6.5 8 33 S1
RST 5.5 9 8085 A 32 RD
INTR 10 31 WR
INTA 11 30 ALE
AD 0 12 29 S0
AD 1 13 28 A15
AD 2 14 27 A14
AD 3 15 26 A13
AD 4 16 25 A12
AD 5 17 24 A11
AD 6 18 23 A10
AD 7 19 22 A9
Vss 20 21 A8

Fig. 2.1: 8085 Pin Configuration

2.3 Signals of 8085

Signals of 8085 can be divided into 6 different categories
1. Address lines/Bus
2. Data lines/Bus
3. Control and Status Signals
4. Power supply and clock signal
5. Externally initiated signals
6. Serial I/P and serial O/P ports
2.3.1 Address Lines
There are 16 address lines in 8085 from AD 0 – AD 7 and from A 8 – A 1 5 . Address lines are
used to identify the memory locations. So, 2 1 6 different memory locations can be identified
with these 16 address lines. Therefore, the maximum size of the memory which can be

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Pins and Signals of 8085 [3]
connected to 8085 is 65536 or 64K where, 1K = 1024 bytes. The lower order address lines
AD 0 – AD 7 are time multiplexed with data lines.
2.3.2 Data Lines
Microprocessor 8085 has 8 data lines from AD 0 – AD 7 . The lower order address lines are
time multiplexed with the data lines. The ALE signal is used to distinguish between lower
order address line and data lines.

2.3.3 Control and Status Signals

Microprocessor 8085 has 2 control signals RD and WR , three status signals ( IO / M , So and S1) and one
special purpose signal (ALE)

i. ALE (Address Latch Enable): It is positive going pulse generated every time when the microprocessor
begins with an operation of reading or writing the data on memory or IO devices. When the signal on
this pin is high the lower order address bus carries the lower order address and when the signal is low
the lower order address bus carries the 8 bit data. The signal is primarily used to latch the low-order
address from the multiplexed bus and generate a separate set of address lines, A7 - A0. Demultiplexed
Address and Data Bus with control signals is shown in Fig. 2.1

ii. RD (Read): It is active low signal. When signal on this pin is low the reading operation is performed
with memory or I/O device.

iii. WR (Write): It is active low signal. When the signal on the pin is low the write operation is performed
with memory or I/O devices.

iv. IO / M : When signal on this pin is high the reading and writing operation is performed with I/O devices and
when it is low the reading and writing operation is performed with memory.

v. S0 and S1 : These are the status signals of 8085 which indicates the status of operation being performed
by microprocessor. Various operations and corresponding status and control signals are shown in Table
2.1.
Note:- No. of control signals = 2 ( RD and WR ).

2.3.4 Power supply and Clock signal

1. VCC : A power supply of +5V.

2. VSS: Ground reference.

3. X1 and X2: A crystal oscillator is connected between X1 and X2. The frequency of crystal oscillator is
divided by 2 internally therefore for 3 MHz operation a crystal of 6MHz should be used.

4. CLK (OUT): The signal on this pin can be used as the system clock for the peripherals to synchronize
their operation with the microprocessor.

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Pins and Signals of 8085 [4]
Table 2.1 : Operation and corresponding status and control signals
Operation IO / M S1 S0 Control Signal
Op code fetch 0 1 1 RD = 0
Memory read 0 1 0 RD = 0
Memory write 0 0 1 WR = 0
IO Read 1 1 0 RD = 0
IO Write 1 0 1 WR = 0
Interrupt 1 1 1 INTA = 0
Acknowledge
Halt Z 0 0 RD = 0
Hold Z X X WR = 0
Reset Z X X INTA = 0

Note : Z= Tristate or high impedance state, X = Unspecified

Note : Tri-state logic devices have three states: logic 1, logic 0, and high impedance.

A 15 A15
A8 A8
ALE Address
AD7 Bus
EN A 7

AD0 Latch A 0

D7
Data Bus
8085 D0

IO / M MEMR
RD
WR MEMW

IOR

IOW

Fig.2.2 : 8085 Demultiplexed Address and Data Bus with control signals

2.3.5 Externally Initiated Signals

1. INTR( Interrupt Request):This is the general purpose interrupt of 8085. When signal on this pin is
made high then it means that the microprocessor is being requested to interrupt the execution of the
program and to call some subroutine.

2. INTA (Interrupt Acknowledge) : The signal is generated by microprocessor in the response to INTR
request.

3. RST 5.5: This pin is used for vectored interrupt RST 5.5. When signal on this pin is high the

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Pins and Signals of 8085 [5]
microprocessor interrupts the execution of the main program and call the subroutine stored at the
starting address 002C H.

4. RST 6.5: This pin is used for RST 6.5 vectored interrupt of 8085. When signal on this pin is made high
the microprocessor call the subroutine stored at 0034 H.

5. RST 7.5: This pin is used for RST 7.5 vectored interrupt of 8085. When signal on this pin is made high
the microprocessor calls the subroutine stored at 003C H.

6.
TRAP: This pin is used for vectored non-maskable Trap interrupt of 8085. When signal on this pin is
made high the processor immediately calls the subroutine stored at the address 0024H.

7. HOLD: (Hold Request): The signal is generated by the peripheral devices such as DMA which
requests the microprocessor to relieve the address and data buses.
DMA (Direct Memory access) : 8237/8257 DMA controller is used for the data transfer between
memory and I/O devices directly. It saves the time of microprocessor.

8. HLDA: (Hold Acknowledge) : The signal is generated by microprocessor in the response to HOLD
request. It is active high signal.

9. READY: The READY signal is an external request from a slow peripheral, to indicate that the
peripheral is not yet ready for data transfer. When this signal is high during the Read or Write cycle, it
indicates that I/O or memory is ready to send or receive data. The 8085 samples the READY line during
T2 of each machine cycle. Then it continues to sample the TW state and adds additional wait states until
the READY signal becomes inactive(i.e high). During this time, the 8085 extends the time of control
signals and preserves the contents of all the buses. When signal on this pin is low mP waits for integral
number of cycles until it goes high. Thus, the READY signal can be used to synchronize the response
time of any type of peripheral.

10. RESET IN : When the signal on this pin is made low the program counter is initiated with 0000H,
address and data buses are tri-stated, interrupt system is disabled and Microprocessor unit (MPU) is
reset

11. RESET OUT: This signal can be used for resetting the peripheral devices connected to the
microprocessor.

2.3.6 Serial I/O ports

1. SID ( Serial Input Data): This pin is used for receiving the data into microprocessor serially. The data
is read into D7 bit of accumulator.

2. SOD (Serial Output Data) : This pin is used for sending the data from microprocessor serially. The
data is sent from D7 bit of accumulator.

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Pins and Signals of 8085 [6]
+ 5 V GND

1 2 40 20
Serial SID 5 X1 X2 VCC VSS
I/O SOD 4
Ports A15 28
High-Order
Address Bus
TRAP 6 21
A8
RST 7.5 7
RST 6.5 8
RST 5.5 9
Externally 10
INTR AD 7
Initiated 19
Signals 8085A Multiplexed
Address/Data
READY 35 AD 0 Bus
HOLD 39 12
RESET IN 36 30 ALE
29
External Signal INTA S0
11 33
Acknowledgment S1
HLDA 38 34 Control
IO/M and
32 Status Signals
RD
31
WR

3 37
RESET CLK
OUT OUT
Note:- Number of output pins = 27
Number of input pins = 21
Number pins of shared between input and output signals = 8 pins

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Pins and Signals of 8085 [7]

OBJECTIVE TYPE PRACTICE QUESTIONS

GATE QUESTIONS
Q.1 Some of the pins of an 8085 CPU and their functions are listed below. Identify the correct answer that
matches the pins to their respective functions
P. RST 7.5 1. Selects IO or memory
Q. HOLD 2. Demultiplexes the address and data
bus
R. IO/ 3. Is a vectored interrupt
S. ALE 4. Facilitates direct memory access
5. Is a clock
6. Selects BCD mode of operation
(a) P-3, Q-2, R-1, S-4 (b) P-4, Q-1, R-5, S-3
(c) P-3, Q-4, R-1, S-2 (d) P-2, Q-3, R-6, S-1
GATE(IN,03)

IES QUESTIONS
Q.2 The frequency of the driving network connected between pins 1 and 2 of a 8085 chip must be
(a) equal to the desired clock frequency (b) twice the desired clock frequency
(c) four times the desired clock frequency (d) eight times the desired clock frequency
IES(E&T,91)
Q.3 Assertion (A) : The data bus and address bus of 8085 microprocessor are multiplexed.
Reason (R) : Multiplexing reduces the number of pins.
(a) Both A and R are true and R is the correct explanation of A
(b) Both A and R are true but R is not a correct explanation of A
(c) A is true but R is false
(d) A is false but R is true
IES(E&T,97)
Q.4 Which one of the following signal combinations will generate MEMR signal ?
(a) IO/M ∧ RD (b) IO/M ∨ RD
(c) IO/M ∨ RD (d) IO/M ∧ RD
IES(EE,00)
Q.5 Which one of the following sets of status signals is used in an 8085 microprocessor to uniquely identify the
seven machine cycles ?
(a) IO/M, RD, WR (b) S1,S0 , INTA
(c) IO/M ,S1,S0 (d) S2, S1, S0

IES(EE,00)
Q.6 The number of output pins of a 8085 microprocessor are
(a) 40 (b) 27
(c) 21 (d) 19

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Pins and Signals of 8085 [8]
IES(EE,02)
Q.7 Which of the following does not take place when 8085 processor is reset ?
(a) 8085 gives reset out signal to reset external hardware
(b) 8085 resets program counter to FFFF H
(c) The interrupt system is disabled
(d) The buses are tri-stated
IES(EE,05)
Q.8 Which signal of 8085 microprocessor is used to insert wait states ?
(a) READY (b) ALE
(c) HOLD (d) INTR
IES(2007/EE/1A(i)/2)
Q.9 Match List-I(Instruction of 8085) with List-II (Function of Instruction) and select the correct answer using
the code given below the Lists :
List-I List-II
A. RST 6.5 1. Highest priority of interrupts
B. INTR 2. Vector interrupt
C. TRAP 3. Interrupt request
D. HLDA 4. Hold acknowledge
Code:
A B C D
(a) 2 4 1 3
(b) 1 3 2 4
(c) 2 3 1 4
(d) 1 4 2 3
IES(E&T,07)
Q.10 In a microcomputer, why are wait states used ?
(a) To make the processor wait during a DMA operation
(b) To make the processor wait during an interrupt processing
(c) To make the processor wait during a power shutdown
(d) To interface slow peripherals to the processor
IES(E&T,07)
Q.11 Which of the following is/are correct statements ?
1. Bus is a group of wires carrying information
2. Bus is needed to achieve reasonable speed of operation.
3. Bus can carry data or address.
4. A bus can be shared by more than one device.
Select the correct answer from the codes given below
(a) 1 only (b) 1 and 2 only
(c) 2, 3 and 4 only (d) 1, 2, 3 and 4
IES (E&T,09)
Q.12 Consider the following statements :
In 8085 microprocessor, data-bus and address-bus are multiplexed in order to
1. Increase the speed of microprocessor.
2. Reduce the number of pins.
3. Connect more peripheral chips.
Which of the above statements is/are correct ?
(a) 1 only (b) 2 only
(c) 2 and 3 (d) 1, 2 and 3

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Pins and Signals of 8085 [9]
IES (EE,09)
Q.13 Match List-I (Microprocessor pin) with List-II (Signals on pin) and select the correct answer using the code
given below the Lists :
List-I List-II
A. TRAP 1. Interrupt
B. HLDA 2. Initializing
C. RESET 3. Enable
D. ALE 4. Memory access
Code :
A B C D
(a) 1 2 4 3
(b) 3 2 4 1
(c) 1 4 2 3
(d) 3 4 2 1
IES (EE,09)
Q.14 If the status of the control lines S1 and S0 is LOW, then 8085 microprocessor is performing:
(a) Reset operation (b) HOLD operation
(c) Halt operation (d) Interrupt acknowledge
IES(EE,11)
Q.15 A bus connected between the CPU and the main memory that permits transfer of information between main
memory and the CPU is known as
(a) DMA bus (b) Memory bus
(c) Address bus (d) Control bus
IES(EE,14)
Q.16 Ready pin of micro-processor is used
(a) To indicate that micro-processor is ready to receive inputs
(b) To indicate that micro-processor is ready to receive outputs
(c) To introduce wait state
(d) To provide direct memory access
IES(EE,14)
Q.17 Consider the following statements regarding RESET instruction of 8085 microprocessor:
1. PC contents become 0000H.
2. All interrupts are enabled.
3. RESET OUT pin is at logic 0.
Which of the above statements is/are correct?
(a) 1 only (b) 2 only
(c) 1 and 2 (d) 2 and 3
IES(E&T,14)
Q.18 In a microprocessor, WAIT states are used to
(a) Make the processor WAIT during a DMA operation
(b) Make the processor WAIT during an interrupt processing
(c) Make the processor WAIT during a power shut down
(d) Interface SLOW peripheral to the processor
IES(E&T,15)
Q.19 Statement (I): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data
transfer or not.
Statement (II): In the microprocessor during data transfer operations, the wait states are added by forcing
the ready signal low.
(a) Statement (I) and Statement (II) are individually true and statement (II) is the correct explanation of

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Pins and Signals of 8085 [10]
statement (II)
(b) Statement (I) and Statement (II) are individually true but statement (II) is not the correct explanation of
statement (I)
(c) Statement (I) is true but statement (II) is false
(d) Statement (I) is false but statement (II) is true
IES(EE,15)
Q.20. To interface a slow memory, wait states are added by
(a) Extending the time of the chip select logic
(b) Causing READY signal to go low
(c) Causing READY signal to go high
(d) By increasing the clock frequency
IES(EE,15)
MISCELLANEOUS QUESTIONS
Q.21 Which one of the following statements is correct?
The ALE line of Intel 8085 microprocessor is used to
(a) latch the output of an I/O instruction into an external latch
(b) deactivate the chip-select signal from memory devices
(c) latch the 8 bits of address lines AD7 – AD0 into an external latch
(d) find the interrupt enable status of the TRAP interrupt
IAS(2007)
Q.22 Which one of the following statements is correct?
In 8085 microprocessor, the READY signal is useful when the CPU communicates with
(a) a PPI chip (b) a DMA controller chip
(c) a slow peripheral device (d) a fast peripheral device
IAS(2006) & IES(E&T,10)
Q.23 Match List-I with List-II and select the correct answer using the code given below the lists :
List-I List-II
A. SID, SOD 1. Wait state
B. READY 2. Interrupt
C. TRAP 3. Serial data transfer
D. ALE 4. Memory of I/O read/write
5. Address latch control
Code :
A B C D
(a) 3 1 5 2
(b) 3 1 2 5
(c) 4 3 2 5
(d) 4 3 1 2
IAS(2007)
Q.24 In the context of 8085 microprocessor, the correct matching combination between Column A and Column
B is
Column-A Column-B
P. ALE 1. Rotate accumulator left
Q. PSW 2. Compare with accumulator
R. CMA 3. Program status word
S. RLC 4. Address latch enable

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Pins and Signals of 8085 [11]
5. Program stack word
6. Arithmetic logic enabled
7. Complement accumulator
8. Rotate accumulator left through carry
(a) P-6, Q-5, R-2, S-8 (b) P-4, Q-3, R-2, S-8
(c) P-4, Q-3, R-7, S-1 (d) P-6, Q-5, R-7, S-1
BSNL-JTO(TC,09)

ANSWERS AND EXPLANATIONS

Q.1 Ans (c)
P. RST 7.5 is a vectored interrupt.
Q. HOLD signal facilitates the direct memory access.
R. IO/ signal selects I/O or memory.
S. ALE signal demultiplexes the address and data bus.
Q.2 Ans (b)
In 8085 microprocessor a crystal (or RC,LC network) is connected between pins 1 & 2. The crystal frequency
is divided by two internally. So, frequency of crystal is twice the operating frequency.
Q.3 Ans (a)
The lower order address bus (AD0 – AD7) is multiplexed with data because it reduces number of pins in the
processor. So, both assertion and reasons are true and reason is correct explanation of assertion.
Q.4 Ans (b)
The logic circuit for generation of control signals is as shown below,

IO/M MEMR

Intel RD
8085 MEMW

WR
IOR

IOW

The MEMR signal is low only when IO / M and RD both are low. So, the condition for generation of this
signal is IO / M ∨ RD .
Q.5 Ans (c)
IO/M , S1,S0 signals are used in an 8085 microprocessor to uniquely identify the seven machine cycles.

M/c
S1 S0 IO/M
Cycle
M1 1 1 0 Op code fetch
M2 1 0 0 memory read
M3 0 1 0 memory write
M4 1 0 1 I/O reads
M5 0 1 1 I/O write
M6 1 1 1 Interrupt Ack
M7 0 0 Z Halt
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Pins and Signals of 8085 [12]
Z = Tri-state or high impedance state
Q.6 Ans (b)
The output pins of a 8085 microprocessor are 27.
Note : 8085 microprocessor has total 40 pins. Out of which 27 pins are output , 21 pins are input and 8 pins
(ADo -AD7) are shared between output and input signals.
Q.7 Ans.(b)
Following events would occur when 8085 microprocessor is reset :
i) Processor gives reset out signal to reset external hardware
ii) Processor resets program counter to 0000H
iii) The interrupt system is disabled
iv) The buses are tristated
Q.8 Ans.(a)
READY signal of 8085 microprocessor is used to insert wait states in 8085 microprocessor.
Q.9 Ans.(c)
A. RST 6.5 is vector interrupt of 8085.
B. INTR signal is used for interrupt request.
C. TRAP has highest priority among all interrupts
D. HLDA is hold acknowledge signal generated in response to HOLD request.
Q.10 Ans.(d)
In a microcomputer, wait states are used to interface slow peripherals to the processor. READY signal used
to provide proper WAIT states when the microprocessor is communicating with a slow peripheral device.
Q.11 Ans.(d)
Facts about a bus,
1. Bus is a group of wires carrying information
2. Bus is needed to achieve reasonable speed of operation.
3. Bus can carry data or address.
4. A bus can be shared by more than one device.
So, all statements are correct.
Q.12 Ans.(b)
The lower order address bus (AD0 – AD7) is multiplexed with data bus because it reduces number of pins
in the processor.
Q.13 Ans.(c)
A. TRAP pin is used for non-maskable vectored interrupt.
B. HLDA is hold acknowledge signal generated in response to HOLD request. The signal is generated by
microprocessor in the response to HOLD request. It is active high signal. It is used by DMA to access
memory directly.
C. RESET is used for initializing the microprocessor operation.
D. ALE is used for enabling the address latch. When this signal is high the signal of AD0 to AD7 lines is
lower order address.
Q.14 Ans.(c)
If the status of the control lines S1 and S0 is LOW, then 8085 microprocessor is performing halt operation.
Q.15 Ans.(d)
A bus connected between the CPU and the main memory that permits transfer of information between main
memory and the CPU is known as Control bus.
Q.16 Ans.(c)
READY pin is used by slow responding peripheral. When signal on this pin is low the microprocessor wait
for integral number of clock cycles until it goes high.
Q.17 Ans.(a)
Following events would occur when 8085 microprocessor is reset :
i) Processor gives reset out signal to reset external hardware. So, RESET OUT pin is at logic ‘0’.
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Pins and Signals of 8085 [13]

ii) Processor resets program counter to 0000H.
iii) All the interrupts are disabled.
iv) The buses are tristated.
Q.18 Ans.(d)
In a microprocessor, WAIT states are used to interface SLOW peripheral to the processor.
Q.19 Ans.(b)
I. Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or
not. Statement I is true.
II. In the microprocessor during data transfer operations, the wait states are added by forcing the ready
signal low. Statement II is also true but it is not correct explanation of Statement I.
Q.20 Ans.(b)
READY pin is used by slow responding peripheral. When signal on this pin is low the microprocessor wait
for integral number of clock cycles until it goes high.
Q.21 Ans.(c)
The ALE line of Intel 8085 microprocessor is used to latch the 8 bits of address lines AD7 – AD0 into an
external latch.
Q.22 Ans.(c)
In 8085 microprocessor, the READY signal is useful when the CPU communicates with a slow peripheral
device.
Q.23 Ans.(b)
A. SID and SOD pins are used for serial data transfer
B. READY pin is used by slow responding peripheral. When signal on this pin is low the microprocessor
wait for integral number of clock cycles until it goes high.
C. TRAP pin is used for non-maskable vectored interrupt.
D. ALE is used enabling the address latch. When this signal is high the signal of AD0 to AD7 lines is lower
order address.
Q.24 Ans.(c)
P. ALE stands for address latch enable
Q. PSW stands for program status word
R. CMA stands for complement accumulator.
S. RLC stands for rotate accumulator left without carry.

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