Embedded Deterministic

Test

By
M. Balakrishna
 INTRODUCTION
•The advantages of EDT Logic are
i) It will reduce the number of ports
ii) Reduce the test time
iii) Reduce the test data volume(compressed version of test
pattern data)
•Limitation of EDT Logic
i)Extra area over head because of decompressor, compressor
and masking logic
ii) More control needed over edt signals edt update, edt
clock.
Block Diagram:
•EDT Components
i) Decompressor – consists of Ring generator and Phase
shifter
 Ring generator generates random patterns, the output of

ring generator is connected to internal scan chains through

more randomness and drives more number of scan chains.

as Masking Gates.
• The first input of AND gate is the output of scan chain and the
second input of AND gate is controlled by masking registers and
Decoder.
• The decoder gives the value of zero if any scan chain output is
X, otherwise it gives a one value .
•If any scan chain output is X ,that particular AND gate output is
zero, in this way the propagation of X is blocked.
• The Ex OR tree is used to compress several scan chains data and
finally it gives less test data volume to scan channel outputs.
•The pipeline flops are added in between Ex OR gates to increase
the data transfer rate.
BYPASS :
• The scan chains are concatenated in to longer scan chains by
disabling the EDT logic.
•The bypass logic is used for debugging purpose.
•In fig. if the selection line of Mux (bypass enable) is one then
the internal scan chains are concatenated in to longer scan
chains.
•The number of bypass chains are equal to the number of
external channels.
EDT Control signals
•EDT clock signal should not be pulsed in capture phase ,the
reason for that is if EDT clock is pulsed in capture the new
data will be pumped in to the scan chains, the previous data
will be replaced with new data so the previous data which is
intended to detect a particular fault that fault can not be
detected.
• EDT update signal is used to reset the LFSR Flops. EDT
Update signal must be high for one cycle in load/unload
phase, so the previous data will be completely shifted out
and new pattern will be loaded.
•Both EDT Clock and EDT Update signals are pulsed in
load/unload phase.
 Example for Test time Reduction
•Test time = No.of patterns* No.of shift cycles per
pattern*scan clock time period
Here No.of shift cycles per pattern is nothing but length of
the scan chain
For Ex:
Without EDT: No of patterns = 20; chain length = 50;scan clock
time period = 1 ns
Test time = 20*50*1 = 1000 ns
With EDT: No of patterns = 25; chain length = 25;scan clock
time period = 1 ns
Test time = 25*25*1 = 625 ns
Example for Test Data Volume Reduction
•Test Data volume = No.of patterns* No.of shift cycles per
pattern*No.of external channels
For Ex:
Without EDT: No of patterns = 20; chain length = 50;No.of
chains =5
Test data volume = 20*50*5 = 5000
With EDT: No of patterns = 25; chain length = 25; No.of
channels =5
Test data volume= 25*25*5 = 3125
So with EDT test time and test data volume will be reduced.
X –Blocking in Compactor
•If any scan chain has X value in any pattern it blocks the
other scan chain value at the same position .This is called X
blocking.
• This X blocking problem can be resolved by using scan chain
masking technique.
•There are two types of scan chain masking
i) one hot masking
ii) flexible masking
•In one hot masking only one scan chain is observed at the
scan channel output and remaining all scan chains are
masked.
•One hot masking is very useful in debugging the serial
patterns.
•The advantage of one hot masking over the edt bypass logic
is it takes less time for debugging but in bypass logic it takes
more time to generate the ATPG bypass patterns and
debugging is also difficult .
•In flexible masking multiple scan chains are observed at the
scan channel outputs.Here xpress compactor is used.The
xpress compactor allows to observe the scan chains which is
having known values and it blocks all other chains which is
having X value.
•The faults which are not detected by flexible masking
patterns are detected by the One hot masking patterns.
Scan chain masking
•In this example in pattern 1, chain 1 is having a value ‘1’ in
first cycle and chain 2 is having a value ‘X’. So the second input
of AND gate of chain 1 is applied as 1 and second input of
AND gate of chain 2 is applied as 0.so chain 2 is blocked in
cycle 1.In cycle 1 only first chain data is observed at scan
channel output .
•The same procedure will be applicable to all cycles of the
pattern of chain 1 and chain 2.
•So chain 1 is blocked in cycles 3 and 6,chain 2 is blocked in
cycles 1,3 and 7.
•Masking code for chain 1 is: 1/1/0/1/1/0/1/1 and chain 2 is :
0/1/0/1/1/1/0/1.
•Channel output is : 1 0 1 1 0 0 1 1.
Fault Aliasing
•If the combinational circuit output is driven to flip flops
located in same position of two different scan chains, if the
good value is 0 then Ex OR operation gives a value 0 at
channel output.
•If fault occurs at the same position means value 1 is loaded
instead of 0,then also the channel output is 0.
•Fault free value and faulty value both are same, so it is not
possible to detect the fault.
•To overcome this fault aliasing problem scan chain masking
technique will be used.
•The solution to this problem is in pattern 1 the first scan
chain data is observed and second chain data is blocked. So
the second input of AND gate of chain 1 is ‘1’ and second
input of AND gate of chain 2 is ‘0’ .
•In second pattern the second scan chain data is observed and
first chain data is blocked. So the second input of AND gate
of chain 2 is ‘1’ and second input of AND gate of chain 1 is ‘0’
.
•In this way both scan chains data is observed at scan channel
output in two different patterns.
 Low Power Test
•Low power test can be done in two phases
i)low power shift
ii) low power capture
•Low power shift:
•Many of the test patterns contains the x values which are not
intended to detect any fault.Only some of the bits contain 1s and
0s,these bits will detect some specific fault.
•Generally the X values are filled with 1s and 0s randomly.so
switching is more and power consumption is more in this case.
•In low power shift, the power controller adds a constant zero
values in place of X ,So the switching activity will be reduced
and power consumption will be reduced.
• For ex: the pattern is 1 0 X X 1 1 ,if these X s are replaced
randomly with 1 0 1 0 1 1.Three times switching will be
done,i.e. 1->0,0->1,1->0.
•If these Xs are replaced with constant zeros 1 0 0 0 1 1.The
no.of switching transitions will be minimised there by
reducing the power
•We enable the power controller logic in EDT phase and
constrain the power shift enable value 1 in ATPG.
•Low power capture:
•It uses the clock gaters which are already available in the
design.
•The clock gaters provides the clock what ever the portion of
the design needs the clock and it turns off the clock where it
is not needed.
•So power consumption will be reduced
Pattern Reordering
•In this example the length of scan chain 1 is 8 and length of
scan chain 2 is 3.Here the last three 5 bits of scan chain 2 is
filled with first 5 bits of the next pattern and then Xor ed
together .
•This procedure is applicable to all the patterns but not to the
last pattern.
•In ATPG the empty bit positions are filled with Xs.
Last pattern Handling
•In last pattern handling the empty bit positions in
unbalanced chains are replaced with the last pattern bits
again.
• In this example the length of chain 1 is 8 and length of chain
2 is 4 .last pattern of scan chain 2 is 1 0 X 1 .The last 4
positions of scan chain 2 is filled with this last pattern 1 0 X 1
again.
•The masking code for scan chain 1 is : 1/0/1/1/1/1/0/1
•The masking code for scan chain 2 is : 1/0/1/1/1/0/1/1
•Scan channel output is : 0 0 1 1 0 1 0 0
THANK YOU