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    ECE657

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    Sneha Pm
    This document summarizes a group project implementing cache coherence for a shared memory multiprocessor (SMP) architecture using the MESI protocol. The group members defined SMP, explained what cache coherence is and why it is important for performance. They described their scenario of two processors with caches connected via a bus to shared memory. The MESI protocol states and implementation were outlined. The project was simulated using Modelsim and results were verified. Future work could include synthesizing and targeting the design to a board.

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    ECE657

    Uploaded by

    Sneha Pm
    47 views15 pages
    This document summarizes a group project implementing cache coherence for a shared memory multiprocessor (SMP) architecture using the MESI protocol. The group members defined SMP, explained what cache coherence is and why it is important for performance. They described their scenario of two processors with caches connected via a bus to shared memory. The MESI protocol states and implementation were outlined. The project was simulated using Modelsim and results were verified. Future work could include synthesizing and targeting the design to a board.

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    This document summarizes a group project implementing cache coherence for a shared memory multiprocessor (SMP) architecture using the MESI protocol. The group members defined SMP, explained what cache coherence is and why it is important for performance. They described their scenario of two processors with caches connected via a bus to shared memory. The MESI protocol states and implementation were outlined. The project was simulated using Modelsim and results were verified. Future work could include synthesizing and targeting the design to a board.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    47 views15 pages

    ECE657

    Uploaded by

    Sneha Pm
    This document summarizes a group project implementing cache coherence for a shared memory multiprocessor (SMP) architecture using the MESI protocol. The group members defined SMP, explained what cache coherence is and why it is important for performance. They described their scenario of two processors with caches connected via a bus to shared memory. The MESI protocol states and implementation were outlined. The project was simulated using Modelsim and results were verified. Future work could include synthesizing and targeting the design to a board.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 15

    Implementing Cache Coherence for a Shared Memory Multiprocessor(SMP) architecture using MESI protocol

    Group Project:ECE 657 Date: 05/11/06 Group members: Brandon Rogers Junkyu Lee Vishnupriya Girinathan

    Introduction
    1.Definition: SMP
    A shared-memory multiprocessor consists of a number of processors accessing one or more shared memory modules. The processors can be physically connected to the memory modules in a variety of ways, but logically every processor is connected to every module.

    2.What is Cache Coherence ?


    When multiple processors with separate caches share a common memory, it is necessary to keep the caches in a state of coherence by ensuring that any shared operand that is changed in any cache is changed throughout the entire system. This is done in either of two ways: through a directory-based or a snooping system.

    3.Why is Cache Coherency an important factor?


    Cache misses and memory traffic due to shared data blocks limit the performance of parallel computing in multiprocessor computers or systems. Cache coherence aims to solve the problems associated with sharing data between multiple processors.

    Shared Memory Multiprocessor: with write back approach


    Our Scenario
    P1 P2

    Cache Controller

    cache

    cache

    Cache Controller

    Bus

    Memory

    The MESI Protocol &Implementation


    MESI is a four state write-back invalidation protocol The four states of MESI are: M-Modified-The cache line is present only in the current cache, and is dirty; it has been modified from the value in main memory.The cache is required to write the data back to main memory at some time in the future, before permitting any other read of the (not longer valid) main memory state. E- Exclusive-The cache line is present only in the current cache, but is clean; it matches main memory. S- Shared-Indicates that this cache line may be stored in other caches of the machine. I- Invalid-Indicates that this cache line is invalid.

    Working of the MESI protocol explained using animation

    Simulation outputs from various modules

    Processor

    Cache Controller Processor Side

    Data Cache

    Cache Controller- Bus Side

    Bus

    Memory

    Conclusions In this project we implemented Cache coherency using the MESI Protocol which is snoop based and using the write back approach.The project was simulated using Modelsim and the results obtained were verified. Future Work This work could be extended by synthesizing it and and targeting it on a board.

    References
    1. 2. https://www.cs.tcd.ie/Jeremy.Jones/vivio/caches/MESIHelp.htm Parallel Computer Architecture, David .E. Culler, Jaswinder Pal Singh with Anoop Gupta, 1999.

    Thanks!!!

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