SPI--- Serial Peripheral Interface

SPI Basics
• The Serial Peripheral Interface (SPI) bus was developed by Motorola

• Serial communication between master and slave devices.

• A communication protocol using 4 wires

• Full-duplex

• Synchronous

• For every clock cycle one bit is transferred

• SPI can be clocked up to 10 MHz

• The SPI bus is commonly used for communication with Flash memory, sensors,
real-time clocks (RTCs), analog-to-digital converters, and more
 SPI
Physical Layer
MOSI MOSI
• At the simplest level, SPI CLK CLK
Slave
Master MISO
communications consists of a single MISO CS
CS
bus master connected to a single
bus slave.
The SPI bus specifies four logic signals:
• One device acts as Master and other
as Slave.
• SCLK : Serial Clock (output from master)
• Multiple slave-devices may be
• MOSI : Master Out Slave In (data output
supported through selection with
from master)
individual chip select (CS), • MISO : Master In Slave Out (data output
sometimes called slave select (SS)
from slave)
lines • SS : Slave Select (often active low, output
• Two data transfer lines.
from master to indicate that data is
being sent)
Physical Layer

• In case of multiple slaves, master

must provide the dedicated chip
select, CS lines for each slave and
this configuration is like the
configuration depicted on the left.
• This configuration is often used in
data acquisition systems where
multiple analog-to-digital (ADCs)
and digital-to-analog converters
(DACs) must be accessed
individually.
 Physical Layer

• Both the SPI master and Slave

have a shift Register.
Physical Layer: Data flow and sequence

 When the master wants to send the

data to the slave, First it loads the
data into its Shift Register.

 The master then select the

destination. This is done by selecting
the SS or CS line associated with that
slave.
 Physical Layer

 The serial Clock line is then enabled

and one bit of the data is shifted on
the MOSI line with each clock pulse.
Physical Layer

 Since the SPI protocol uses full

duplex synchronous serial data
transfer method, it could transfer
the data and at the same time
receiving the slave data using its
internal shift register.

 From the SPI master and slave

interconnection diagram on the
right side, You can see that the SPI
peripheral use the shift register to
transfer and receive the data
 Bit Transfer

• For example the master want to transfer

0b10001101(0x8E) to the slave and at the same time
the slave device also want to transfer the
0b00110010(0×32) data to the master.

• By activating the CS (chip select) pin on the slave

device, now the slave is ready to receive the data.

• Prior to a data exchange, the master and slave

load their internal shift registers with memory
data.

• Upon a clock signal, the master clocks out its shift

register MSB first via MOSI line.

• At the same time the slave reads the first bit from the
master at MOSI, stores it into memory, and clocks
out its MSB via MISO.
 Bit Transfer
cont...

SP
I

• Continuously using the same principle for each

bit, the complete data transfer between master and
slave will be done in 8 clock cycle
 SPI

• SPI interface allows to transmit and receive data simultaneously on two lines (MOSI
and MISO).

• Clock polarity (CPOL) and clock phase (CPHA) are the main parameters that
define a clock format to be used by the SPI bus.
 • Idle (or First) State is 0 so the Polarity =0
Clock Polarity

Polarity determines the idle state of

the clock.

• Idle (or First) State is 1 so the Polarity =1

• If Idle state is low then Clock Polarity=0.

• If Idle state is high then Clock Polarity=1

Clock Phase
Phase determines at which edge data read/write occurs

• If Clock Polarity=0 and data read/write occurs at falling

edge then the Clock Phase=1

• If Clock Polarity=0 and data read/write occurs at rising

edge then the Clock Phase=0.

• If Clock Polarity=1 and data read/write occurs at rising

edge then the Clock Phase=1

• If Clock Polarity=1 and data read/write occurs at falling

edge then the Clock Phase=0
Modes in SPI

• The frame of the data exchange is described

by two parameters, the clock polarity
(CPOL) and the clock phase (CPHA).

• This diagram shows the four possible states

for these parameters and the corresponding
mode in SPI.
Mode 0
• The data must be available before the
first clock signal rising.

• The clock idle state is zero.

• The data on MISO and MOSI lines

must be stable while the clock is high
and can be changed when the clock is
low.

• The data is captured on the clock's

low-to-high transition and
propagated on high-to-low clock
transition.
 Mode 1

• The first clock signal rising can be used

to prepare the data.

• The clock idle state is zero.

• The data on MISO and MOSI lines must

be stable while the clock is low and can
be changed when the clock is high.

• The data is captured on the clock's

high-to-low transition and
propagated on low-to-high clock
transition.
 Mode 2

• The data must be available before the

first clock
signal falling.

• The clock idle state is one.

• The data on MISO and MOSI

lines must be stable while the
clock is low and can be changed
when the clock is high.

• The data is captured on the clock's

high-to-low transition and
propagated on low-to-high clock
transition.
Mode 3
• The first clock signal falling can
be used to prepare the data.

• The clock idle state is one.

• The data on MISO and MOSI

lines must be stable while the
clock is high and can be changed
when the clock is low.

• The data is captured on the clock's

low-to-high transition and
propagated on high-to-low clock
transition.
 Why 4 modes why not only 1

• SPI's predecessor had only one CPOL/CPHA mode.

• SCK(Clock) negative polarity is best when open-L type drivers

with pullup are used.

• SCK(Clock) positive polarity is good when bus master is powered separately as SCK will
not glitch when master is power up/down.

• CPHA=1 is useful when MISO is multiplexed with BUSY/READY and CPHA=0

require 1 less flipflop in a slave.
How to Select the Mode

• You select the mode by configuring a bit in a configuring register. Your device
manual will tell you which bit it is

• As for how to configure clock phase and polarity, it depends on the device you are
working with.

• Typically the device has a register with bits corresponding to clock phase and
polarity this bit can be manipulated to bring the device in the desired mode.
Advantages of SPI

1. Full duplex communication

2. Higher throughput than I²C protocol

3. Not limited to 8-bit words in the case of bit-transferring

4. Arbitrary choice of message size, contents, and purpose

5. Simple hardware interfacing

6. Typically lower power requirements than I²C due to less circuitry.

Disadvantages of SPI

1. Requires more pins on IC packages than I²C

2. No hardware flow control

3. No Acknowledgement Signal.
 I2C SPI
multi slave, multi master multi slave, single master
I2C vs SPI
half duplex communication full duplex communication
2 wire 4 wire
speed varies according to the 5 possibility of speed is above
modes of operation 100MHz
slower than SPI faster than I2C
draws more power draws less power
less expensive than SPI more expensive than I2C
acknowledgement based no acknowledgement
authentication of data receipt
uses frames to separate data of 12-16 bit can also be
messages sent
wire and logic interface with a no pull up register
pull-up register
Thank you!