Lect# 12-2, Floyd, CH # 09

Digital
Fundamentals
Tenth Edition
Floyd
Chapter 9
© 2008 Pearson Education

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Basic Shift Register Operations
A shift register is an
arrangement of flip-flops
with important applications
in storage and movement of
data. Some basic data
movements are illustrated
here.
Summary
Serial-in/Serial out Shift Register
Shift registers are available in IC form or can be
constructed from discrete flip-flops as is shown here with a
five-bit serial-in serial-out register.
Each clock pulse will move an input bit to the next flip-
flop. For example, a 1 is shown as it moves across.
FF0 FF1 FF2 FF3 FF4

Serial 1 1 1 1 1 1 Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 data
input output
C C C C C
CLK
CLK
Summary
A Basic Application
An application of shift registers is conversion of serial
data to parallel form.
For example, assume the binary number 1011 is loaded
sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.
FF0
FF0 FF1
FF1 FF2
FF2 FF3
FF3
Serial
Serial 1
X
0 1
0 10
1 10 11
data
data D00
D Q00
Q D11
D Q11
Q D22
D Q22
Q D33
D Q33
Q
input
input
C
C C
C C
C C
C
CLK
CLK
CLK
Summary
Bidirectional Shift Register
Bidirectional shift registers can shift the data in either
direction using a RIGHT/LEFT input.
The logic analyzer simulation shows a bidirectional shift register
such as the one shown in Figure 9-19 of the text. Notice the HIGH
level from the Serial data in is shifted at first from Q3 toward Q0.
CLK
RIGHT/LEFT Shift left Shift right
Serial data in
Q0
Q1
Q2
Q3
Summary
Basic Shift Register Operations
A shift register is an arrangement of flip-flops with
important applications in storage and movement of data.
Some basic data movements are illustrated here.
Data in
Data in Data out Data out Data in Data out
Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out
Data in
Data in
Data out Data out

Serial in/parallel out Parallel in/parallel out Rotate right Rotate left
Summary
Universal Shift Register
A universal shift register has both serial and parallel
input and output capability. The 74HC194 is an example
of a 4-bit bidirectional universal shift register.
D0 D1 D2 D3
(3) (4) (5) (6)

(1)
CLR SRG 4
(9)
S0
(10)
S1
(2)
SR SER
(7)
SL SER
(11)
CLK C
(15) (14) (13) (12)
Q0 Q1 Q2 Q3
Summary
Shift Register Counters
Shift registers can form useful counters by recirculating
a pattern of 0’s and 1’s. Two important shift register
counters are the Johnson counter and the ring counter.
FF0 FF1 FF2 FF3
The Johnson counter can D0 Q0 D1 Q1 D2 Q2 D3 Q3
be made with a series of D C C C C
flip-flops Q3 Q3
CLK
… or with a series of J-K J0

FF0
Q0 J1
FF1
Q1 J2
FF2
Q2 J3
FF3
Q3
Q3
flip flops. Here Q3 and Q3

C C C C
are fed back to the J and K K0 Q0 K1 Q1 K2 Q2 K3 Q3
Q3
inputs with a “twist”.

CLK
Summary
Johnson Counter
Redrawing the same Johnson counter (without the clock
shown) illustrates why it is sometimes called as a “twisted-
ring” counter.
FF0
J0 Q0
“twist” C
K0 Q0
Q3
Q3
Q3
Q3
K1
J1
C
FF3
FF1
C
Q1
Q1
J3
K3
2 Q 2 K
2 Q 2 J
2 FF
Summary
Johnson Counter
The Johnson counter is useful when you need a sequence
that changes by only one bit at a time but it has a limited
number of states (2n, where n = number of stages).
The first five counts for a 4-bit Johnson counter that is
initially cleared are: CLK Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
What are the remaining 3 states? 7 0 0 0 1
Summary
Ring Counter
The ring counter can also be implemented with either D
flip-flops or J-K flip-flops.
FF0 FF1 FF2 FF3
Here is a 4-bit ring counter D0 Q0 D1 Q1 D2 Q2 D3 Q3

Q3
constructed from a series C C C C
of D flip-flops. Notice the

feedback. CLK
FF0 FF1 FF2 FF3
Like the Johnson counter, J0 Q0 J 1 Q1 J 2 Q2 J 3 Q3

Q3
it can also be implemented C C C C
with J-K flip flops. K0 Q0 K1 Q1 K2 Q2 K3 Q3

Q3
CLK
Summary
Ring Counter
Redrawing the Ring counter (without the clock shown)
shows why it is a “ring”.
FF0
The disadvantage to this counter J0 Q0
is that it must be preloaded with C
the desired pattern (usually a K0 Q0
single 0 or 1) and it has even

fewer states than a Johnson
Q3
Q3
Q3
Q3
K1
J1
C
counter (n, where n = number of
FF3
FF1
C
Q1
Q1
3
K3
J
flip-flops.
On the other hand, it has the 2 Q 2 K
advantage of being self-decoding C
with a unique output for each state. 2 Q 2 J
2 FF
Summary
Ring Counter
A common pattern for a ring counter is to load it with a single 1 or a
single 0. The waveforms shown here are for an 8-bit ring counter
with a single 1.
CLK 1 2 3 4 5 6 7 8 9 10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

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© 2008 Pearson Education

FF0 FF1 FF2 FF3 FF4

Data in Data out Data out Data in Data out

Data out Data out

(3) (4) (5) (6)

be made with a series of D C C C C

… or with a series of J-K J0

flip flops. Here Q3 and Q3

inputs with a “twist”.

Here is a 4-bit ring counter D0 Q0 D1 Q1 D2 Q2 D3 Q3

constructed from a series C C C C

of D flip-flops. Notice the

FF0 FF1 FF2 FF3

Like the Johnson counter, J0 Q0 J 1 Q1 J 2 Q2 J 3 Q3

it can also be implemented C C C C

with J-K flip flops. K0 Q0 K1 Q1 K2 Q2 K3 Q3

is that it must be preloaded with C

the desired pattern (usually a K0 Q0

single 0 or 1) and it has even

advantage of being self-decoding C

with a unique output for each state. 2 Q 2 J

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