Programmable Logic

Devices
PLD
• A programmable logic device (or PLD) is a general name for a digital
integrated circuit capable of being programmed to provide a variety of
different logic functions.
• Simple combinational PLDs are capable of realizing from 2 to 10
functions of 4 to 16 variables with a single integrated circuit. More
complex PLDs may contain thousands of gates and flip-flops.
• Thus, a single PLD can replace a large number of integrated circuits, and
this leads to lower cost designs.
• When a digital system is designed using a PLD, changes in the design can
easily be made by changing the programming of the PLD without having
to change the wiring in the system.
Programmable Logic Arrays
• A programmable logic array (PLA) performs the same basic function as a ROM.
• A PLA with n inputs and m outputs can realize m functions of n variables. The
internal organization of the PLA is different from that of the ROM. The decoder is
replaced with an AND array which realizes selected product terms of the input
variables. The OR array ORs together the product terms needed to form the output
functions, so a PLA implements a sum-of-products expression, while a ROM directly
implements a truth table.

Programmable Logic Array Structure

• Figure shows Product terms are formed in the AND array by connecting switching
elements at appropriate points in the array. For example, to form A′B′, switching
elements are used to connect the first word line with the A′ and B′ lines.
Switching elements are connected in the OR array to select the product terms
needed for the output functions

PLA with Three Inputs, Five Product Terms, and

• The input side of the table specifies the product terms. The symbols 0, l, and – indicate
whether a variable is complemented, not complemented, Or not present in the corresponding
product term. The output side of the table specifies which product terms appear in each output
function. A 1 or 0 indicates whether a
given product term is present or not
present in the corresponding output
function. Thus, the first row of Table 9-1
indicates that the term A′B′ is present in
output functions F0 and F2, and the
second row indicates that AC′ is
present in F0 and F1.

And-Or Equivalent
• f1 = Σ m(2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
• f2 = Σ m(2, 3, 5, 6, 7, 10, 11, 14, 15)
• f3 = Σ m(6, 7, 8, 9, 13, 14, 15)
• f1 = a′bd + abd + ab′c′ + b′c
• f2 = c + a′bd
• f3 = bc + ab′c′ + abd PLA table
• we can construct a PLA table, Figure with one row for each distinct
product term.
• Figure shows the corresponding PLA structure, which has four inputs,
six product terms, and three outputs. A dot at the intersection of a
word line and an input or output line indicates the presence of a
switching element in the array.
PLA structure
• To determine the value of fi for a given input combination, the values
of fi in the selected rows of the PLA table must be ORed together. The
following examples refer to the PLA table of Previous Figure .
• If abcd = 0001, no rows are selected, and all f ’s are 0. If abcd = 1001,
only the third row is selected, and f1 f2 f3 = 101. If abcd = 0111, the
first, fifth, and sixth rows are selected. Therefore, f1 = 1 + 0 + 0 = 1, f2
= 1 + 1 + 0 = 1, and f3 = 0 + 0 + 1 = 1.
Programmable Array Logic
• The PAL (programmable array logic) is a special case of the programmable logic array in
which the AND array is programmable and the OR array is fixed. The basic structure of
the PAL is the same as the PLA shown in Figure

• Because only the AND array is programmable, the PAL is less expensive than the more
general PLA, and the PAL is easier to program.
• For this reason, logic designers frequently use PALs to replace individual logic gates
when several logic functions must be realized.
• Figure represents a segment of an unprogrammed PAL.
• The symbol represents an input buffer which is logically
equivalent to
• A buffer is used because each PAL input must drive many AND gate
inputs. When the PAL is programmed, some of the interconnection
points are programmed to make the desired connections to the AND
gate inputs. Connections to the AND gate inputs in a PAL are
represented by X’s as shown:
• When designing with PALs, we must simplify our logic equations and
try to fit them into one (or more) of the available PALs. Unlike the
more general PLA, the AND terms cannot be shared among two or
more OR gates; therefore, each function to be realized can be
simplified by itself without regard to common terms. For a given type
of PAL, the number of AND terms that feed each output OR gate is
fixed and limited. If the number of AND terms in a simplified function
is too large, we may be forced to choose a PAL with more gate inputs
and fewer outputs.
• As an example of programming a PAL, we will implement a full adder.
The logic equations for the full adder are
• Sum = X′Y′Cin + X′YC′in + XY′C′in + XYCin
• Cout = XCin + YCin + XY
• Figure 9-33 shows a section of a PAL where each OR gate is driven by
four AND gates. The X’s on the diagram show the connections that are
programmed into the PAL to implement the full adder equations. For
example, the first row of X’s implements
• the product term X′Y′Cin.
Implementation of a Full Adder
Using a PAL
Complex Programmable Logic
Devices
• Instead of a single PAL or PLA on a chip, many PALs or PLAs can be placed on a single
CPLD chip and interconnected. When storage elements such as flip-flops are also
included on the same IC, a small digital system can be implemented with a single CPLD.
• This CPLD has four function blocks, and each block has 16 associated macrocells (MC1,
MC2, . . .). Each function block is a programmable AND-OR array that is configured as a
PLA.
• Each macrocell contains a flip-flop and multiplexers that route signals from the function
block to the input-output (I/O) block or to the interconnect array (IA). The IA selects
signals from the macrocell outputs or I/O blocks and connects them back to function
block inputs.
• Thus, a signal generated in one function block can be used as an input to any other
function block. The I/O blocks provide an interface between the bi-directional I/O pins
on the IC and the interior of the CPLD.
basic architecture of a Xilinx
XCR3064XL CPLD
Basic architecture of a Xilinx
XCR3064XL CPLD
• CPLD has four function blocks, and each block has 16 associated macrocells
(MC1, MC2, . . .). Each function block is a programmable AND-OR array that
is configured as a PLA.
• Each macrocell contains a flip-flop and multiplexers that route signals from
the function block to the input-output (I/O) block or to the interconnect
array (IA).
• The IA selects signals from the macrocell outputs or I/O blocks and
connects them back to function block inputs. Thus, a signal generated in
one function block can be used as an input to any other function block.
• The I/O blocks provide an interface between the bi-directional I/O pins on
the IC and the interior of the CPLD.
how a signal generated in the PLA is
routed to an I/O pin through a macrocell.
• Any of the 36 outputs from the IA (or their complements) can be connected to
any inputs of the 48 AND gates. Each OR gate can accept up to 48 product
term inputs from the AND array.
• The macrocell logic in this diagram is a simplified version of the actual logic.
The first MUX (1) can be programmed to select the OR-gate output or its
complement.
• The MUX (2) at the output of the macrocell can be programmed to select
either the combinational output (G) or the flip-flop output (Q). This output
goes to the interconnect array and to the output cell.
• The output cell includes a three-state buffer (3) to drive the I/O pin. The buffer
enable input can be programmed from several sources. When the I/O pin is
used as an input, the buffer must be disabled.
Field-Programmable Gate Arrays

• An FPGA is an IC that contains an array of identical logic cells with

programmable interconnections.
• The user can program the functions realized by each logic cell and the
connections between the cells.
• The interior of the FPGA consists of an array of logic cells, also called
configurable logic blocks (CLBs). The array of CLBs is surrounded by a
ring of input-output interface blocks. These I/O blocks connect the
CLB signals to IC pins. The space between the CLBs is used to route
connections between the CLB outputs and inputs.
layout of part of a typical FPGA
Simplified version of a CLB
• This CLB contains two function generators, two flip-flops, and various
multiplexers for routing signals within the CLB.
• Each function generator has four inputs and can implement any function of up to
four variables. The function generators are implemented as lookup tables (LUTs).
• A four-input LUT is essentially a reprogrammable ROM with 16 1-bit words. This
ROM stores the truth table for the function being generated.
• The H multiplexer selects either F or G depending on the value of H1.
• The CLB has two combinational outputs (X and Y) and two flip-flop outputs (XQ
and YQ). The X and Y outputs and the flip-flop inputs are selected by
programmable multiplexers.
• The select inputs to these MUXes are programmed when the FPGA is configured.
• For example, the X output can come from the F function generator, and the Y
output from the H multiplexer.
Implementation of a function
generator with inputs a, b, c, d.
• The functions
Decomposition of Switching
Functions
• In order to implement a switching function of more than four variables using 4- variable function
generators, the function must be decomposed into subfunctions where each subfunction requires
only four variables.
• One method of decomposition is based on Shannon’s expansion theorem. We will first illustrate this
theorem by expanding a function of the variables a, b, c, and d about the variable a:

•
• (1)
K-map for equation (1)
• The left half of the map where a = 0 is in effect a 3-variable map for f0(b, c, d). Looping terms on the left half
gives f0 = c′d′ + b′c + cd, which is the same as the previous result. Similarly the right half where a = 1 is a 3-
variable map for f1(b, c, d), and looping terms on the right half gives f1 = c′ + bd. The expressions for f0 and
f1 obtained from the map are the same as those obtained algebraically in Equation
 General form of Shannon’s expansion
theorem
• The general form of Shannon’s expansion theorem for expanding an n-
variable function about the variable xi is
• f(x1, x2, . . . , xi–1, xi, xi+1, . . . , xn) = xi′ f(x1, x2, . . . , xi–1, 0, xi+1, . . . , xn) + xi f(x1, x2, . . . , xi–1, 1, xi+1, . . . , xn)
= xi′ f0 + xi f1 ------------------------- (2)

• where f0 is the (n − 1)-variable function obtained by setting xi to 0 in the

original function and f1 is the (n − 1)-variable function obtained by setting
xi to 1 in the original function. The theorem is easily proved for switching
algebra by first setting xi to 0 in Equation (2), and, then, setting xi to 1.
Because both sides of the equation are equal for xi = 0 and for xi = 1, the
theorem is true for switching algebra.
• Applying the expansion theorem to a 5-variable function gives f(a, b, c, d, e) = a′ f(0, b, c, d, e) + a f(1, b,
c, d, e) = a′ f0 + a f1 ------------------------- (3)
• This shows that any 5-variable function can be realized using two 4-variable function generators and a
2-to-1
• To realize a 6-variable function using 4-variable function generators, we apply the expansion theorem
twice:
• G(a, b, c, d, e, f ) = a′G(0, b, c, d, e, f ) + a G(1, b, c, d, e, f ) = a′G0 + a G1
• G0 = b′G(0, 0, c, d, e, f ) + b G(0, 1, c, d, e, f ) = b′G00 + b G01
• G1 = b′G(1, 0, c, d, e, f ) + b G(1, 1, c, d, e, f ) = b′G10 + bG11
• Because G00,G01,G10, and G11 are all 4-variable functions, we can realize any 6-variable function using
four 4-variable function generators and three 2-to-1 MUXes, . Thus, we can realize any 6-variable
function using two CLBs . Alternatively, we can write
• G(a, b, c, d, e, f ) = a′b′G00 + a′b G01 + ab′G10 + ab G11----------------------------- (4)
• and realize G using four function generators and a 4-to-1 MUX. In general, we can realize any n-variable
function (n > 4) using 2n−4 4-variable function generators and one 2n−4-to-1 MUX. This is a worst-case
situation because many functions of n- variables can be realized with fewer function generators.