Programmable Logic Devices

What are Programmable Logic Devices?

Specialised integrated circuits, consisting of an array of logic cells that can be interconnected by programming to realize different digital designs.
Interconnections are programmed using electrically programmable switches

Vendors produce a single standard device that users program to perform their required function
Programming is typically performed by design developers at their site, with no IC masking steps Largest devices are now 10M gates (10*10^6)

Programmable Logic Devices

Read Only Memories (ROMs) Programmable Logic Arrays (PLAs) Programmable Array Logic Devices (PALs)

Combinational PLDs
PROM is a combinational programmable logic device (PLD). - SRAM/DRAM ? A combinational PLD is an integrated circuit with programmable gates divided into an AND array and an OR array to provide an AND-OR sum of product implementation. The major types of combinational PLDs differ in the placement of the programmable connections in the AND-OR array.

Combinational PLDs

Combinational PLDs
PROM has a fixed AND array constructed as a decoder and programmable OR array. The programmable OR gates implement the Boolean functions in sum of minterms. PAL has a programmable AND array and a fixed OR array. The AND gates are programmed to provide the product terms for the Boolean functions, which are logically summed in each OR gate. PLA has a programmable AND and OR arrays. The product terms in the AND array may be shared by any OR gate to provide the required sum of products implementation.

Programmable Logic Array (PLA)

The PLA is similar to the PROM in concept The product terms are connected to OR gates to provide the sum of products for the required Boolean functions.

PLA
PLA with 3 inputs, 4 product terms, and 2 outputs.

Uses the array logic graphic symbols

Programmable polarity feature

PLA
Each input and its complement are connected to the inputs of each AND gate. Outputs of the AND gates are connected to the inputs of each OR gate. The output of the OR gate goes to an XOR gate where the other input can be programmed to receive a signal equal to either logic 1 or 0. The output is inverted when the XOR input is connected to 1. The output does not change when the XOR input is connected to 0.
x 1 x' and x 0 x F1 AB' AC A' BC' F 2 ( AC BC)'

PLA
Programming Table for the PLA:

PLA
The fuse map of a PLA can be specified in a tabular form. The PLA table consists of 3 sections.
1st section lists the product terms numerically. 2nd section specifies the required paths between inputs and AND gates. 3rd section specifies the paths between the AND and OR gates.

For each output variable, we can have a T (for true) and C (for complement) for programming the XOR gate.

PLA
The size of PLA is specified by the number of inputs, number of product terms, and number of outputs. A typical integrated PLA may have 16 inputs, 48 product terms and 8 outputs.

PLA
PLA may be mask programmable or field programmable (FPLA Field Programmable Logic Array). When implementing a combinatorial circuit with a PLA, number of distinct product terms must be reduced, since a PLA has a finite number of AND gates. This can be done by simplifying each Boolean function to a minimum number of terms.

PLA
Implement the following two boolean functions with a PLA:

F1 ( A, B, C ) (0,1,2,4)

F2 ( A, B, C ) (0,5,6,7)

PLA
Implement the following three boolean functions with a PLA:

F1 m( 2, 3, 5, 7, 8, 9, 10 , 11, 13 , 15 ) F2 m( 2, 3, 5, 6, 7, 10 , 11, 14 , 15 ) F3 m( 6, 7, 8, 9, 13 , 14 , 15 ) F1 bd b' c ab' F2 c a' bd

Eight different product terms

F3 bc ab' c' abd are required!?

For PLA we want to minimize the total number of product terms, not the number of product terms for each function separately!

PLA
ab

cd
00

00

01

11

10 1

cd

ab

00

01

11

10

cd

ab

00

01

11

10 1

00

00 1 1 1 1 1 F2 1 1 1 1 01 11 10 1 1 F3 1 1 1

01
11 1 1

1 1

1 1

1 1 1

01
11

10

10

F1

ab' c' b' c a' bd bc abd

PLA
F1 a' bd abd ab' c' b' c F2 a' bd b' c bc F3 abd ab' c' bc

PLA
nMOS NOR Gate

F0 m( 0, 1, 4, 6 ) A' B' AC'

PLA
PLA density is not big as it seems

F0 m( 0, 1, 4, 6 ) A' B' AC' F1 m( 2, 3, 4, 6, 7 ) B AC' F2 m( 0, 1, 2, 6 ) A' B' BC' F3 m( 2, 3, 5, 6, 7 ) AC B

PLA: 3 inputs, 5 p.t., 4 outputs

PLA
AND-OR Array Equivalent

PLAs are not very popular nowadays

Combinational PLDs

Programmable Array Logic (PALs)

PAL is a PLD with a fixed OR array and a programmable AND array. Since only AND gates are programmable, the PAL is easier to program and fast but is not flexible as PLA. Figure shows the logic configuration of a typical PAL. (4 I/Ps and 4 O/Ps). Each input has a buffer-inverter gate and each output is generated by a fixed OR gate. There are 4 sections, each being composed of a 3 wide AND-OR array(meaning 3 programmable AND gates in each section and one fixed OR gate).

Programmable Array Logic (PALs)

Programmable Array Logic (PALs)

Programmable AND plane and fixed OR plane.

PALs have a built-in circuit to initialize all registers to zero.

Programmable Array Logic (PALs)

A typical PAL IC may have 8 inputs, 8 outputs, and 8 sections, each consisting of an 8-wide AND-OR array. Output terminals are sometime driven by 3state buffers or inverters. When designing a PAL, the Boolean function must be simplified to fit into each section. Unlike the PLA, a product term cannot be shared among two or more gates. Therefore, each function can be simplified by itself without regard to common product terms.

Programmable Array Logic (PALs)

Unprogrammed

Programmed

Using PALs: An Example

x1 x2 x3

Implement the following:

f1 x1x2 x' 3 x'1 x' 2 x3 f2 x'1 x' 2 x1x2 x3
P1

P2

P3

P4

AND plane

Using PALs: An Example

x1 x2 x3

f1 x1x2 x' 3 x'1 x' 2 x3 f2 x'1 x' 2 x1x2 x3

P1 f1 P2

P3 f2 P4

AND plane

Using PALs
The number of product terms in each section is fixed, and if the number of terms in the function is too large it may be necessary to use two sections to implement one Boolean function. Consider the following example:
w( A, B, C , D) (2,12,13)

w ABC' A' B' CD '

x A BCD x( A, B, C , D) (7,8,9,10,11,12,13,14,15) y A' B CD B' D'

z ( A, B, C , D) (1,2,8,12,13) y ( A, B, C , D) (0,2,3,4,5,6,7,8,10,11,15)

z ABC' A' B' CD ' AC' D' A' B' C ' D w AC' D' A' B' C ' D

Using PALs
PAL Programming Table:

Using PALs

Sequential PLDs
Digital systems are designed using flip-flops and gates. Since the combinatorial PLD consists of only gates, it is necessary to include external flip-flops when they are used in design. Sequential programmable devices include both gates and flip flops. In this way, the device can be programmed to perform a variety of sequential circuit functions. The major types are:
Sequential programmable logic devices (SPLD) Complex Programmable Logic Device (CPLD) Field Programmable Gate Array (FPGA)

Sequential PLDs
Sequential PLD is sometimes referred to as a simple PLD to differentiate it from the complex PLD. SPLD includes flip-flops within the integrated circuit chip in addition to the AND-OR array. A PAL or PLA is modified by including a number of flip-flops connected to form a register. The circuit output can be taken from the OR gates or from the outputs of flip-flops. Additional programmable connections are available to include the flip-flops (D or JK type) outputs in the product terms formed with the AND array.

Sequential PLDs

Sequential PLDs
The configuration mostly used for SPLD is the combinatorial PAL together with D flip-flops. A PAL that includes flip-flops is referred to as a registered PAL. Each section of an SPLD is called a macrocell. A macrocell is a circuit that contains a sum-ofproducts combinational logic function and an optional flip-flop. A typical SPLD has from 8 to 10 macrocells within one IC package.

Sequential PLDs
A typical macrocell can have the following programming options
Ability to either use or bypass the flip-flop Selection of clock edge polarity Selection of preset and clear for the register Selection true and complement of an output. An XOR gate is used to program a true/complement condition.

Multiplexers are used to select between two or four distinct paths by programming the selection inputs.

PALs
Classification of PAL Devices - Combinational PALs - Sequential PALs - Arithmetic PALs Most Popular Series 20 and series 24 PAL devices

Combinational PAL devices

NAND-NAND, OR-NAND, NOR-OR expressions can be implemented with active high output devices NAND-AND, OR-AND and NOR-NOR expressions can be implemented with active low output devices Number of product terms is limited just like in PLAs (typically 8) Number of inputs to OR gate(fixed) is also limited (2, 4, 8 or 16)

Series 20 PALs
Combinational PAL devices PAL10H8 PAL10L8 PAL16C1 PAL12H6 PAL12L6 PAL14H4 PAL14L4 PAL16H2 PAL16L2 General naming convention PALxYz x - Number of inputs to AND array (vs dedicated i/ps) Y - Output type z - Number of outputs (approx. = No. of Macrocells)

Series 20 PALs
Output types (Y) H - Active high (OR gate) L - Active Low (NOR gate) C - true and complement output available Eg: PAL16H8 16 inputs to AND array 10 dedicated inputs (+ 6 feedback inputs) 8 outputs Output is an OR gate (active high) Number of product term per OR gate is 8 (typical value)

Increment 1 0 First fuse numbers 0 32 64 96 128 160 192 224 4 8 12 16 20 24 28

19

Series 20 PALs PAL16H8

256 288 320 352 384 416 448 480 3

18

512 544 576 608 640 672 704 736 4

17

768 800 832 864 896 928 960 992 5

16

1024 1056 1088 1120 1152 1184 1216 1248 6

15

1280 1312 1344 1376 1408 1440 1472 1504 7

14

1536 1568 1600 1632 1664 1696 1728 1760 8

13

1792 1824 1856 1888 1920 1952 1984 2016 9 Note: Fuse number = first fuse number + increment 11

12

Series 20 PALs
Sequential PAL devices

PAL16L8 PAL16R8 PAL16R6 PAL16R4

PAL16L4 PAL16H4 PAL16P8

R - Registered output P - Programmable I/O

Series 20 PALs: Typical output structures

Sequential PAL devices

PAL16L8 - No flip flops : but outputs are fed back to input side PAL16R4 - 4 registered outputs 4 outputs not registered 8 dedicated inputs 8 feedback inputs OE, CLK, Vcc, GND Typically 8 product terms per OR gate

PAL16L8 - Logic Diagram

PAL16L8 - Logic Diagram

Logic Diagram for 16R4 PAL

Logic Diagram for 16R4 PAL

Arithmetic PAL devices

Outputs of 2 or more OR gates fed to EX-OR gate so that arithmetic functions can be easily generated PAL16A4 and PAL16X4 devices
1 2 3

P1 P2 P3 P4

Simple ALUs can easily be implemented

Series 24 PALs
24 pin versions of PAL devices Typically 10 inputs and 10 outputs PAL12L10 PAL20C1 PAL14L8 PAL20L10 PAL16L6 PAL20X10 PAL18L4 PAL20X8 PAL20L2 PAL20X14 PAL22V10 - most popular among all PAL devices V - versatile output

PAL22V10
General features 22 inputs and 10 outputs All 10 outputs go through OLMC 12 dedicated inputs (including a clock) 8 to 16 product terms per OR gate Typical input to output delay of 5/10 ns Reprogrammable version: PALCE22V10

PAL22V10

Functional Diagram

PAL22V10

PAL22V10

OLMC of PAL22V10
Output Logic MacroCell (OLMC) is a standard design used in most of the PLDs

TI Design

OLMC of PAL22V10
OLMC output options

OLMC of PAL22V10
OLMC output options

PAL
Designing Circuits with PAL devices is also an automated process (most of the cases)

One can use VHDL, Verilog, ABEL(advanced Boolean Expression Language), PALASM or similar language to do this If you dont like using CAD tools you have the option of representing your design as a programming table
But before using a PAL/ and PLD its better to be familiar with the internal details of the device so that one can optimally use a PAL ( or any PLD for that reason) Dont use a PAL to design an f= ax + ax !

CPLDs

CPLDs

CPLDs
The design of a digital system using PLD often requires the connection of several devices to produce the complete specification. For these type of applications, Complex Programmable Logic Devices (CPLD) are more suitable. A CPLD is a collection of individual PLDs on a single integrated circuit. A programmable interconnection structure allows the PLDs to be connected to each other in the same way that can be done with the individual PLDs.

How to expand PLD architecture?

Increase # of inputs and outputs in a conventional PLD?
E.g., 16V8 --> 20V8 --> 22V10. Why not --> 32V16 --> 128V64 ?

Problems:
n times the number of inputs and outputs requires n2 as much chip area -- too costly logic gets slower as number of inputs to AND array increases

Solution: multiple PLDs with a relatively small programmable interconnect.

Less general than a single large PLD, but can use software fitter to partition the design into smaller PLD blocks.

CPLDs

I/O Blocks provide the connection to IC pins. Each I/O pin is driven by a tri-state buffer and can be programmed to act as input or output.

CPLDs
The switch matrix receives inputs from the I/O block and directs it to the individual macrocells. Similarly, selected outputs from macrocells are sent to the outputs as needed. Each PLD typically contains from 8 to 16 macrocells. The macrocells within each PLD are usually fully connected. If a macrocell has unused product terms they can be used by other nearby macrocells.

CPLD - Structure
General concept: many PLD devices on one IC
I/O b lock I/O b lock

In practice:

PLD b lock

PLD b lock

I/O b lock

more product terms; more routing resources; more macro cells; greater connectivity between macro cells allows implementation of wider more complex functions.

Interconnection wires

I/O b lock

PLD b lock

PLD b lock

CPLD Manufactures
1) Altera

2) Xilinx

Just like TI and ADI in DSP market

CPLD families
Identical individual PLD blocks replicated in different family members.
Different number of PLD blocks Different number of I/O pins

Many CPLDs have fewer I/O pins than macrocells

Buried Macrocells -- provide needed logic terms internally but these outputs are not connected externally. IC package size dictates # of I/O pins but not the total # of macrocells. Typical CPLD families have devices with differing resources in the same IC package.

FPGAs
Historically, FPGA architectures and companies began around the same time that of CPLDs FPGAs are closer to programmable ASICs -- large emphasis on interconnection routing
Timing is difficult to predict -- multiple hops vs. the fixed delay of a CPLDs switch matrix. But more scalable to large sizes.

FPGA programmable logic blocks have only a few inputs and 1 or 2 flip-flops, but there are a lot more of them compared to the number of macrocells in a CPLD.

Classification of PLDs

FPGA - General Structure

Logic block Interconnection switches I/O b lock

I/O block

I/O block

I/O b lock

Classification of FPGAs
I. Based on Granularity 1. Coarse Grained (SRAM Based) - e.g. Altera, Xilinx
Large complex logic blocks Dedicated functions, fast carry etc. Re-programmable Unpredictable propagation delays

2. Fine Grained (Antifuse Based) - e.g. Actel

Sea of small logic blocks Predictable propagation delays High performance timing One time programmable (OTP)

Antifuse FPGAs
Advantages Highest density - a mere cross point - 10X the density of SRAM Lowest switch resistance - 25 Ohms Very low capacitance 1 fF per node.- approaching the metal line capacitance non- volatile Nearly impossible to reverse engineer Radiation hard - Space appns Live within 1 millisecond of the power supply reaching spec voltage Software is easy to place and route Disadvantages Requires programmer Requires a socket - a problem for devices with > 200 pins Those who design by test will throw out a lot of parts. Requires one to two transistors per wire for programming Some antifuse defects not testable until programming

Classification of FPGAs
II. Based on how logic is organised

Xilinx family of FPGAs

Virtex IV (2004 End) Virtex II Pro Virtex II Spartan 3 (1.2V) Spartan 2E (1.8V) Spartan 2 (2.5V) Spartan XL (3.3V) XC4000 XC3000 XC2000 (1985)

General Architecture of Xilinx FPGAs

Xilinx calls the logic cells as CLBs

XC4000 Programmable Switch Matrix

programmable switch element

After Programming