EEE241 Digital Logic Design (DLD)

Lecture 15 – Combinational Circuits

Dr. Muhammad Rizwan Azam

COMSATS University Islamabad (CUI) Islamabad, Pakistan.
 Lecture Outline

• Combination Circuit (Adder)

• Half Adder
• Full Adder
• Binary Adder
• Carry Propagation
• Decimal Adder
• Subtractor
 Design Procedure
 BCD-to-Excess 3 Converter
C C
A B C D w x y z
0 0 0 0 0 0 1 1 1 1 1
0 0 0 1 0 1 0 0 1 1 1 1
x x x x B x x x x B
0 0 1 0 0 1 0 1 A A
1 1 x x 1 x x
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 D D
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x B x x x x B
1 0 1 1 x x x x A 1 x x A 1 x x
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x
 Design Procedure

• The expressions may be manipulated algebraically for the

purpose of using common gates for two or more outputs
 Design Procedure
 BCD-to-Excess 3 Converter

A B C D w x y z
A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
0 1 0 1 1 0 0 0 B

0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x Eastern Mediterranean
x = B’(C+D) + B(C+D)’
University z = D’
1 1 1 1 x x x x 5 / 65
 BCD to Seven-Segment
Decoder a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
d g
0 0 1 0 1101101 y ? e
0 0 1 1 1111001 f
z g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx 1 1 1
x x x x x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx
z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...
 Binary Adder

• Most basic arithmetic operation is the addition of two binary

digits
• Subtraction and Multiplication follows ‘Adder’
• Suppose, we need to add two bits
• I/ps = 2 bits (x, y)
• O/ps?(How many bits required to store result)

• Ans: 2 bits (Carry, Sum) (C,S)

 Half Adder
 Adds 1-bit plus 1-bit
x S
 Produces Sum and Carry
y
HA
C

x
x y C S + y
───
0 0 0 0
C S
0 1 0 1
1 0 0 1
x S
1 1 1 0

C
y

S represents LSB
 Full Adder (Intro)

• Let us analyze if HA can fulfill our requirements

1 1 1 1 1 1
1 1 1 1 0 1
+ 1 0 1 1 1

1 0 1 0 1 0 0

• Limitation of HA is that it can handle only 2 bits

• We need an adder which can add 3 bits (2 significant bits + 1
bit previous carry)
• Need for Full Adder
 Full Adder
 Adds 1-bit plus 1-bit plus 1-bit
x S
 Produces Sum and Carry y FA
z C

x
+ y
x y z y + z
C S
0 0 0 0 0 0 1 0 1 ───
0 0 1 0 1 x 1 0 1 0 C S
0 1 0 0 1 z
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1
1 0 1 1 0 0 0 1 0
1 1 0 1 0 x 0 1 1 1
1 1 1 1 1 z
C = xy + xz + yz
 Full Adder

S = xy'z'+x'yz'+x'y'z+xyz = x  y  z x S
C = xy + xz + yz y FA C
z
 Full Adder
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C z
z
y
z

Implementation of full
adder in sum-of-
 Full Adder

S=xyz x S
C = xy + (x  y)z
y FA C
z

Implementation of full adder with two half adders and an OR

 Full Adder using HAs

x S
y HA HA

z C

x
S

y
C

z
 Binary Adder
x3x2x1x0 y3y2y1y0
c3 c 2 c 1 .
+ x 3 x2 x1 x0
Carry
Cy Binary Adder C0 + y3 y2 y1 y0
Propagate
Addition ────────
Cy S3 S2 S1
S3S2S1S0 S0
x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0
 Binary Adder (Observation)

x3x2x1x0 y3y2y1y0

C4 Binary Adder C0 =0

S3S2S1S0

• How many I/ps? = 9

• The design of this cct. by classical method would require a
truth table with 29 = 512 entries
• Using an iterative method of cascading a standard function, a
simple implementation is possible
Carry Propagation

NOT available immediately

Available
 Carry Propagation

• Problem Statement:
• The signal must propagate through the gates before the correct
output sum is available at O/p
• The longest propagation delay time in an adder is the time it
takes the carry to propagate through FAs
• Example:
• Inputs A3 and B3 are available as soon as I/p signals are applied
to the adder
• However, C3 is not available for a while (C3 depends on C2 and so
on C1 …)
• Time taken in addition operation is critical because other
arithmetic operations → addition
 Carry propagation

• The signal from the input carry Ci to the output carry Ci+1
propagates through an AND gate and an OR gate, which
constitute two gate levels.
• (A1, B1, C1) → C2 → C3 → C4 → (C5, S4)
• When 4-bits full-adder → 8 gate levels (n-bits: 2n gate levels)
 Carry Look-ahead Adder

• Reduce the carry propagation delay

• Employ faster gates (physical circuits have their limits)
• Look-ahead carry (more complex mechanism, yet faster)
• Define two new variables
• Carry propagate: Pi = AiÅBi

• Carry generate: Gi = AiBi

• Sum: Si = PiÅCi
• Carry: Ci+1 = Gi+PiCi
• C0 = Input carry
• C1 = G0+P0C0
• C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0
• C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0
 Carry Look-ahead Adder

• Logic diagram
 1-bit Adder with Carry
Lookahead
• P0 = A0ÅB0 G0 = A0B0
• S0 = P0ÅC0

P0
Carry S0
G0 Generator C0

C0
 Carry Look-ahead Adder

• 4-bit carry-look ahead

adder
• Propagation delay of C3,
C2 and C1 are equal.
 Binary Subtractor

Half Subtractor x D
y HS
x B
- y
───
B D
x y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Full Subtractor
x
- y
x D - z
y FS B ───
z
B D
x y z D B y
0 0 0 0 0 0 1 0 1
0 0 1 1 1 x 1 0 1 0
0 1 0 1 1 z
0 1 1 0 1 D = xy'z'+x'yz'+x'y'z+xyz = x  y  z
1 0 0 1 0 y
1 0 1 0 0
1 1 0 0 0 0 1 1 1
1 1 1 1 1 x 0 0 1 0
z
B = x'y + x'z +
yz