Logic Design

Combinational Circuits
Introduction
▪ Two classes of logic circuits:
❖ combinational
❖ sequential

▪ Combinational Circuit:

inputs Combinational outputs

:: Logic
::

Each output depends entirely on the immediate

(present) inputs.
Introduction
▪ Sequential Circuit: (to be covered later)

inputs Combinational outputs

:: Logic
::

Memory
Output depends on both present and past inputs.
Memory (via feedback loop) contains past
information.
Analysis Procedure
▪ Given a combinational circuit, can you analyze its
function?
A A+B
B F1 = (A+B).(A'+B')

F2 = (A'+B')' = A.B
A'+B'

▪ Steps:
❖ 1. Label the inputs and outputs.
❖ 2. Obtain the functions of
intermediate points and the outputs.
❖ 3. Draw the truth table.
❖ 4. Deduce the functionality of the circuit  half adder.
Design Methods
▪ Different combinational circuit design methods:
❖ Gate-level method (with logic gates)
❖ Block-level design method

▪ Design methods make use of logic gates and useful

functional blocks.
❖ These are available as Integrated Circuit (IC) chips.
Design Methods
▪ Type of IC chips (based on packing density) :
❖ Small-scale integration (SSI): up to 12 gates
❖ Medium-scale integration (MSI): 12-99 gates
❖ Large-scale integration (LSI): 100-9999 gates
❖ Very large-scale integration (VLSI): 10,000-99,999 gates
❖ Ultra large-scale integration (ULSI): > 100,000 gates

▪ Main objectives of circuit design:

❖ (i) reduce cost
reduce number of gates (for SSI circuits)
reduce IC packages (for complex circuits)
❖ (ii) increase speed
❖ (iii) design simplicity (reuse blocks where possible)
Gate-level (SSI) Design: Half Adder
▪ Design procedure:
1) State Problem
Example: Build a Half Adder to add two bits
2) Determine and label the inputs & outputs of circuit.
Example: Two inputs and two outputs labelled, as
follows:

X Half S
Y Adder C
(X + Y)
3) Draw truth table.
Gate-level (SSI) Design: Half Adder
4) Obtain simplified Boolean function.
Example: C = XY
S = X'Y + XY' = X⊕Y

5) Draw logic diagram.

X
S
Y
Half Adder

C
Gate-level (SSI) Design: Full Adder
▪ Half-adder adds up only two bits.
▪ To add two binary numbers, we need to add 3
bits (including the carry).
▪ Example:

▪ Need Full Adder (so called as it can be made from

two half-adders).
X
Full S
Y
Z Adder C
(X + Y + Z)
Gate-level (SSI) Design: Full Adder
▪ Truth table:
Note:
Z - carry in (to the current
position)
C - carry out (to the next position)
C
YZ
X
00 01 11 10
0 1

▪ Using K-map, simplified SOP

1 1 1 1

form: YZ
00
S
01 11 10
X
C = XY + XZ + YZ 0 1 1
S = X'Y'Z + X'YZ'+XY'Z'+XYZ 1 1
1
Gate-level (SSI) Design: Full Adder
▪ Alternative formulae using algebraic manipulation:
C = XY + XZ + YZ
= XY + (X + Y)Z
= XY + ((X⊕Y) + XY)Z
= XY + (X⊕Y)Z + XYZ
= XY + (X⊕Y)Z

S = X'Y'Z + X'YZ' + XY'Z' + XYZ

= X'(Y'Z + YZ') + X(Y'Z' + YZ)
= X'(Y⊕Z) + X(Y⊕Z)'
= X⊕(Y⊕Z) or (X⊕Y)⊕Z
Gate-level (SSI) Design: Full Adder
▪ Circuit for above formulae:
C = XY + (X⊕Y)Z
S = (X⊕Y)⊕Z

X (X⊕Y)
Y S

(XY)

Z
Full Adder made from two Half-Adders (+ OR gate).
Gate-level (SSI) Design: Full Adder
▪ Circuit for above formulae:
C = XY + (X⊕Y)Z Block diagrams.
S = (X⊕Y)⊕Z

X (X⊕Y)
X Sum X
Y Y Sum S
Y
Half Half
Adder Adder
(XY)
Carry Carry
C

Z
Full Adder made from two Half-Adders (+ OR gate).
Block-Level Design Method
▪ More complex circuits can also be built using
block-level method.
▪ In general, block-level design method (as opposed to
gate-level design) relies on algorithms or formulae of
the circuit, which are obtained by decomposing the
main problem to sub-problems recursively (until
small enough to be directly solved by blocks of
circuits).
▪ Simple examples using 4-bit parallel adder as
building blocks:
❖ (1) 16-Bit Parallel Adder
❖ (2) Adder cum Subtractor
4-bit Parallel Adder
▪ Cascading 4 full adders via their carries, we get:
Y4 X4 Y3 X3 Y2 X2 Y1 X1
C4 C3 C2

C5 FA FA FA FA C1

S4 S3 S2 S1
Input
Output
Parallel Adders
▪ Note that carry propagated by cascading the carry
from one full adder to the next.
▪ Called Parallel Adder because inputs are presented
simultaneously (in parallel). Also, called Ripple-Carry
Adder.
16-bit Parallel Adder
▪ Larger parallel adders can be built from smaller ones.
▪ Example: a 16-bit parallel adder can be constructed
from four 4-bit parallel adders:
X16..X13 Y16..Y13 X12..X9 Y12..Y9 X8..X5 Y8..Y5 X4..X1 Y4..Y1
4 4 4 4 4 4 4 4

C17 4-bit // C13 4-bit // C9 4-bit // C5 4-bit // C1

adder adder adder adder
4 4 4 4

S16..S13 S12..S9 S8..S5 S4..S1

A 16-bit parallel adder

16-bit Parallel Adder
▪ Shortened notation for multiple lines.

4 is a shortened
notation for
S4 .. S1 S4 S 3 S2 S 1

16-bit parallel adder ripples carry from one 4-bit block to the
next.
Such ripple-carry circuits are “slow” because of long delays
needed to propagate the carries.
4-bit Parallel Adder cum Subtractor
*Optional
▪ Subtraction can be performed through addition using
2s-complement numbers.
▪ Hence, we can design a circuit which can perform
both addition and subtraction, using a parallel adder.
X4 X3 X2 X1 Y4 Y3 Y2 Y1

4-bit adder
S: control signal
cum subtractor for add/subtract

Result: either X+Y or X-Y

4-bit Parallel Adder cum Subtractor
▪ The control signal S=0 means add
S=1 means subtract
▪ Recall that:
X-Y = X + (-Y)
= X + (2’s complement of Y)
= X + (1’s complement of Y) +1
X+Y = X + (Y)
4-bit Parallel Adder cum Subtractor
▪ Design requires:
(i) XOR gates:

Y Y Y Y'
S=0 S=1

such that: output = Y when S=0

= Y' when S=1

(ii) S connected to carry-in.

4-bit Parallel Adder cum Subtractor
▪ Adder cum subtractor circuit:
Y4 Y3 Y2 Y1
S
X4 X3 X2 X1

C Cout 4-bit Cin

parallel adder Analysis:
If S=1, then
X + (1's complement of Y) +1
S4 S3 S2 S1 appears as the result.
A 4-bit adder cum subtractor If S=0, then X+Y appears as
the result.
Arithmetic Circuits: Adders
Revision
▪ Half adder
Σ
X Σ Sum
Input Output
bits bits
Y Cout Carry

x
y' x'
S = xy' + x'y y'
x' S = (C+x'y')'
y x
y C
x
y C

x
y x
S=x⊕y
S = (x+y)(x'+y') y
x'
y'
C
x
y C
Arithmetic Circuits: Adders
Revision
▪ Full adder Σ
A Σ Sum
Input Output
B
bits Cout Carry bits
Cin

yz yz
X' x
00 01 11 10 x
00 01 11 10
y'
z 0 1 0 1 1
x'
y 1 1 1 1 1 1 1
z'
S C = xy + xz + yz S = x'y'z + x'yz' + xy'z' + xyz
x
y'
z'
x
y x⊕y
z x
y S = (x⊕y)⊕z
x
xy
y
C = xy + (x⊕y)z
x
z C z
y
z
Arithmetic Circuits: Parallel Adders
Revision
▪ Example: Adding two 4-bit numbers
2 ways:
u Serial (one FA)
u Parallel (n FAs for n bits)

Y4 X4 Y3 X3 Y2 X2 Y1 X1
C4 C3 C2

C5 FA FA FA FA C1

Binary Σ
no. A X 4-bit S4 S3 S2 S1
S sum
Binary
no. B Y
Cout Output carry
Input carry Cin
Arithmetic Circuits: Cascading Adders
Revision
▪ 4-bit parallel adder:
❖ cascade 4 full adders

▪ Cascading method can be extended to larger

numbers, example: 16-bit parallel adder.
X16..X13 Y16..Y13 X12..X9 Y12..Y9 X8..X5 Y8..Y5 X4..X1 Y4..Y1
4 4 4 4 4 4 4 4

C17 4-bit // C13 4-bit // C9 4-bit // C5 4-bit // C1

adder adder adder adder
4 4 4 4

S16..S13 S12..S9 S8..S5 S4..S1

Arithmetic Circuits: Adder-Subtractor
Revision
▪ Make use of 2’s complement:
X - Y = X + (-Y)
▪ 2’s complement of Y = Inverting bits in Y and plus 1.
Y4 Y3 Y2 Y1
S
X4 X3 X2 X1 Zi = S.Yi' + S'.Yi
Z4 Z3 Z2 Z1

4-bit When S=0,

C Cout Cin
parallel adder Cin=0, Zi = Yi  S = X + Y
When S=1,
Cin=1, Zi = Yi'  S = X + Y' + 1
S4 S3 S2 S1