Microcontroller

 A microcontroller (MCU) is a small computer on a single integrated

circuit that is designed to control specific tasks within electronic
systems. It combines the functions of a central processing unit (CPU),
memory, and input/output interfaces, all on a single chip.
 Microcontrollers are widely used in embedded systems, such as home
appliances, automotive systems, medical devices, and industrial
control systems. They are also used in consumer electronics products,
such as gaming systems, digital cameras, and audio players.
 A typical microcontroller consists of a processor core, volatile and
non-volatile memory, input/output peripherals, and various
communication interfaces. The processor core is responsible for
executing instructions and controlling the other components of the
microcontroller. The memory is used to store data and program code,
while the input/output peripherals are used to interact with the
external environment.
 8051 microcontroller
 The 8051 is an 8-bit microcontroller with 8 bit data bus and 16-bit address bus.
 The 16 bit address bus can address a 64K byte code memory space and a separate
64K byte of data memory space.
 The 8051 has 4K on chip read only code memory and 128 bytes of internal RAM.
 Besides internal RAM, the 8051 has various Special Function Registers (SFR)
such as the Accumulator, the B register, and many other control registers.
 34 - 8-bit general purpose registers in total.
 The ALU performs one 8-bit operation at a time.
 Two 16 bit timers /Counter
 3 internal interrupts (one serial), 2 external interrupts.
 Four 8-bit I/O ports
 Some 8051 chips come with UART for serial communication and ADC for analog
to digital Conversion
 Comparisons of Microcontroller and Microprocessor:

Microprocessor Microcontroller

A microprocessor is a general purpose A microcontroller is a dedicated chip

which
device which is called a CPU
is also called single chip computer.

A microcontroller includes RAM, ROM,

A microprocessor do not contain on chip
serial and parallel interface, timers,
I/O Ports, Timers, Memories etc.
interrupt circuitry (in addition to CPU) in a
single chip.

Microprocessors are most commonly Microcontrollers are used in small,

used as the CPU in microcomputer minimum component designs performing
systems. control-oriented applications.
Microprocessor instructions are mainly Microcontroller instructions are both bit
nibble or byte addressable. addressable as well as byte addressable.

Microprocessor based system design is Microcontroller based system design is

complex and expensive rather simple and cost effective

The Instruction set of microprocessor is The instruction set of a Microcontroller is

complex with large number of very simple with less number of
instructions. instructions. For, ex: PIC microcontrollers
have only 35 instructions.

A microprocessor has zero status flag. A microcontroller has no zero flag.

Pin diagram of 8051
Summerized block diagram
Internal architecture of 8051
Registers and memory
organization
Registers and memory
organization
Registers and memory
organization
 ADDRESSING MODES &
INSTRUCTIONS SET OF
8051 MICROCONTROLLER
 Addressing modes
 Definition:-

The different ways in which a

source operand in an instruction are known
as the addressing modes.
The 8051 provides a total of 5
distinct addressing modes.
 Types of Addressing modes

Addressing modes

Immediate Register Direct Register indirect Indexed

Addressing mode Addressing mode Addressing mode Addressing mode Addressing mode
Immediate addressing mode
In this addressing mode the
source operand is constant. In immediate
addressing mode, when the instruction is
assembled, the operand comes
immediately after the op-code.
 Continue…

 The immediate data must be

preceded by ‘#’ sign.

 This addressing mode can be used to

load information into any of the
register, including the DPTR.
 Continue…
 Ex :-

MOV A,#25H // load 25H in to A

MOV R4,#62 // load the
decimal value 62
into R4.
MOV DPTR,#4532H // DPTR=4532H.
 Register addressing mode
Register addressing mode
involves the use of registers to hold
the data to be manipulated.
 Continue…
 Ex :-
MOV A,R0 // copy the contents of R0 in to
A.
MOV R2,A // copy the contents of A in to
R2.
ADD A,R5 // add the content of R5 to
content of A.
 Direct addressing mode
In direct addressing mode, the
data is in a RAM memory location whose
address is known, and this address is given
as a part of the instruction. Contrast this
with the immediate addressing mode in
which the operand itself is provided with the
instruction.
 Direct addressing mode
 In this mode the operand is specified by
an 8-bit address field In the instruction.
 One can access all the 128 bytes of
internal RAM locations and each SFR.
 If the MSB bit = 0 then the location is
within on chip internal RAM. If MSB bit = 1
then the location is SFR.

22
 Direct addressing mode
 The location 00h to 7Fh to address the
internal RAM .
 SFR addresses from 80h to FF h

 e.g. MOV A,40h

MOV R0,14h

23
 Continue…
 Ex:-
MOV R0,40H // save content of RAM
location 40h into R0.
MOV 56H,A // save content of A in
RAM location 56H.
 Register indirect addressing mode

 In the register indirect addressing mode,

a register is used as a pointer to the data.
 If the data is inside the CPU, only register
R0 and R1 are used for this purpose.
 In other words,R2-R7 cannot be used to
hold the address of an operand located in
RAM when using this addressing mode.
 Continue…
When R0 and R1 are used as pointers ,
that is, when they hold the address of
RAM locations , they must be preceded
by the “@” sign.
Note : only register R0 and R1 can be used
for indirect addressing mode .
MOV A,@R2 invalid instruction.
 Continue…
Ex :-
MOV A,@R0 // move contents of RAM
location whose address
is held by R0 into A.
MOV @R1,B // move contents of B to
RAM location whose
address is held by R1
 External addressing mode
or Indexed addressing mode
(a) Code access (ROM access)
 Using these instructions only program memory
can be accessed.

 This addressing mode is preferred for reading

look up tables in the program memory.

 Either DPTR or PC can be used as pointer.

31
 External addressing mode
or Indexed addressing mode
 E.g.
MOVC A,@A+DPTR

MOVC A,@A+PC

33
 External addressing mode
or Indexed addressing mode
(b) Data access (RAM access)

 Using this addressing mode the programmer

can access the external Data memory

 E.g. MOVX A,@DPTR

MOVX @R0,A

Prof. Nitin Ahire 34

 Continue…
 In this instruction the content of A are
added to the 16-bit register DPTR to form
the 16-bit address of the needed data.
 Instruction set of 8051
8051 has simple instruction set in
different groups. There are:
 Arithmetic instructions
 Logical instructions
 Data transfer instructions
 Branching and looping instructions
 Bit control instructions
 Arithmetic instructions
These instructions are used to
perform various mathematical operations
like addition, subtraction, multiplication, and
division etc.
 Continue…
 ADD A, R1 // Add the content of
register1 to Accumulator
 ADDC A,#2 // Add 2 to accumulator with
carry
 SUBB A,R2 // Subtract content of register2
from Accumulator
 Continue…
 INC A // Increment accumulator
 DEC A // Decrement accumulator

 MUL AB // Multiply A and B

 DIV AB // Divide A by B
 Logical instructions
 The logical instructions are the instructions
which are used for performing some
operations like AND, OR, NOT, X-OR and
etc., on the operands.
 Continue…
 ANL A, Rn // AND register to accumulator
 ORL A, Rn // OR register to accumulator
 XRL A, Rn // Exclusive OR Reg to Acc
 CLR A // Clear Accumulator
 CPL A // Complement Accumulator
 Data Transfer Instructions
 These instruction are used to transfer the
data from source operand to destination
operand. All the store, move, load,
exchange input and output instructions
belong to this to this group.
 Continue…
 MOV A, Rn // Move Reg to Acc
 MOVX A,@DPTR // Move external RAM
to Accumulator
 PUSH direct // PUSH direct byte on
to stack
 POP direct // POP direct byte from
stack
 Branch and Looping Instructions
 These instructions are used for both
branching as well as looping.
 These instructions include conditional &
unconditional jump or loop instructions.
 Conditional Jump Instructions
 JC // Jump if carry equal to one
 JNC // Jump if carry equal to zero
 JB // Jump if bit equal to one
 JNB // Jump if bit equal to zero
 JBC // Jump if bit equal to one and clear
bit
 Continue…
 JZ // Jump if A=Zero
 JNZ // Jump if A not equal to zero
 DJNZ // Decrement and Jump if not
equal to zero.
 Unconditional Jump Instructions
 In 8051 there two unconditional jumps.
They are:
 SJMP // Short jump
 LJMP // Long jump
 Simple program: Sum of 8-bit Numbers
Stored in Memory

 ORG 00H
MOV R0,50H ;get memory location in memory pointer R0
MOV R1,51H ;get memory location on memory pointer
register R1
MOV A,@R0 ;get content of memory location 50H to
accumulator
ADD A,@R1 ;add content of A with content of memory
location 51H and store result in A
MOV R0,52H ;get 52H to memory pointer R0
MOV@R0,A ;copy content of A to memory location 52H
END
Multiplication and Division
Program

 ORG 00H
MOV A,51H ;get content of memory location 51H to accumulator
MOV 0F0H,52H;get content of memory location 52H to B register
MUL AB ;multiply content of A with content of B
MOV 53H,A ;get lower order byte of product in memory location 53H
MOV54H,0F0H ;get higher order byte of product in memory location
in 54H
MOV A,51H ;get content of memory location 51H to accumulator
MOV 0F0H,52H ;get content of memory location 52H to register B
DIV AB ;divide content of register A with register B
MOV 55H,A ;Copy quotient of result to memory location 55H
MOV 56H,0F0H ;copy remainder of result to memory location 56H
END
 The two legal operations that can be done with B register
is MUL AB and DIV AB. For using any other operation we
must use address of B register 0F0H.

Note: After executing MUL AB Instruction the lower byte

of 16-bit product is left in Accumulator and the high order
byte in register B. If the product is greater than 255(FFH)
the overflow(OV) flag is set; otherwise it is cleared.

For example, the largest possible product is FE01H when

both A and B contain FFH. That is A contains 01H and
register B contains FEh after multiplication of FFH by FFH.
The OV flag is set to 1 to indicate that register B contains
the high-order byte of the product; carry flag is zero.
RISC
 Characteristic of RISC –
1. Simpler instruction, hence simple instruction
decoding.
2. Instruction comes undersize of one word.
3. Instruction takes a single clock cycle to get
executed.
4. More general-purpose registers.
5. Simple Addressing Modes.
6. Fewer Data types.
7. A pipeline can be achieved.
ARM Architecture
 ARM (Advanced RISC Machine)
 A simple but powerful design
 A whole family of designs sharing
similar design principles and a
common instruction set
ARM history
 1983 developed by Acorn computers
 To replace 6502 in BBC computers
 Match the needs for generalized SoC for reasonable power,
performance and die size
 The first commercial RISC implementation
 1990 ARM (Advanced RISC Machine), owned by Acorn, Apple and
VLSI
 One of the most licensed and thus widespread processor cores in
the world
 Used in PDA, cell phones, multimedia players, handheld game console,
digital TV and cameras
 ARM7: GBA, iPod
 ARM9: NDS, PSP, Sony Ericsson, BenQ
 ARM11: Apple iPhone, Nokia N93, N800
 90% of 32-bit embedded RISC processors till 2009
 Used especially in portable devices due to its low power
consumption and reasonable performance
Naming ARM
 ARMxyzTDMIEJFS
 x: series
 y: MMU
 z: cache
 T: Thumb
 D: debugger
 M: Multiplier
 I: Embedded ICE (built-in debugger hardware)
 E: Enhanced instruction
 J: Jazelle (JVM)
 F: Floating-point
 S: Synthesiziable version (source code version for EDA
tools)
Popular ARM Architectures
 ARM7TDMI
 3 pipeline stages (fetch/decode/execute)
 High code density/low power consumption
 One of the most used ARM-version (for low-end systems)
 All ARM cores after ARM7TDMI include TDMI even if they
do not include TDMI in their labels
 ARM9TDMI
 Compatible with ARM7
 5 stages (fetch/decode/execute/memory/write)
 Separate instruction and data cache
 ARM11
• 8 stage pipleine
ARM family comparison

Year 1995 1997 1999

2003
ARM is a RISC
 RISC: simple but powerful instructions that execute
within a single cycle at high clock speed.
 Four major design rules:
 Instructions: reduced set/single cycle/fixed length
 Pipeline: decode in one stage/no need for microcode
 Registers: a large set of general-purpose registers
 Load/store architecture: data processing instructions apply
to registers only; load/store to transfer data from memory
 Results in simple design and fast clock rate
 The distinction blurs because CISC implements RISC
concepts
ARM design philosophy
 Small processor for lower power
consumption (for embedded system)
 High code density for limited memory and
physical size restrictions
 The ability to use slow and low-cost
memory
 Reduced die size for reducing
manufacture cost and accommodating
more peripherals
ARM features
 Different from pure RISC in several ways:
 Variable cycle execution for certain instructions:
multiple-register load/store (faster/higher code density)
 Inline barrel shifter leading to more complex
instructions: improves performance and code density
 Thumb 16-bit instruction set: 30% code density
improvement
 Conditional execution: improve performance and code
density by reducing branch
 Enhanced instructions: DSP instructions
 ARM architecture

 Load/store architecture
 A large array of uniform registers
 Fixed-length 32-bit instructions
 3-address instructions
ARM architecture
Registers
 Only 16 registers are visible to a specific
mode. A mode could access
 A particular set of r0-r12
 r13 (sp, stack pointer)
 r14 (lr, link register)
 r15 (pc, program counter)
 Current program status register (cpsr)
 SPSR
 The uses of r0-r13 are orthogonal
General-purpose registers
31 24 23 16 8 0
15 7
8-bit Byte
16-bit Half word

32-bit word

•6 data types
(signed/unsigned)
•All ARM operations are
32-bit. Shorter data types are
only supported by data transfer
operations.
 Program counter

• Store the address of the instruction to be executed

• All instructions are 32-bit wide and word- aligned

• Thus, the last two bits of pc are undefined.

Current Program status register (CPSR)

mode
overflow bits
Thumb
carry/borro state FIQ
w zero disable
negativ IRQ
e disable
Processor modes
Register organization
Instruction sets
• ARM/Thumb/
Jazelle
Pipeline
ARM7
ARM9
In execution, pc always 8 bytes
ahead
 Pipeline

• Execution of a branch or direct

modification of pc causes ARM core to
flush its pipeline
• ARM10 starts to use branch prediction
• An instruction in the execution stage will
complete even though an interrupt has
been raised. Other instructions in the
pipeline are abondond.
Interrupts
Vector table

Interrupt
handlers

code
Interrupts
Addressing modes
1. Immediate addressing mode
2. Register addressing mode
3. Direct addressing mode
4. Indirect addressing mode
5. Register relative indirect addressing mode
6. Based indexed indirect addressing mode
7. Base with scaled index indirect addressing mode
With examples.
Thank you