PIC16F - Serial

communication

LECTURE 10
Serial I/O Interface
Functional Units 2

Translates data between Translates the TTL-

the internal computer level signals processed
form and the form in by the ACIA into a form
which it is transmitted suitable for the
over the data link transmission path
Types of serial communication

 Twotypes of serial communications are used one is

synchronous and other one Asynchronous.
 Asynchronous communication, there will be no clock
signal required to send and receive data. Start bit and
stop bit is used to validate data between transmitter
and receiver.
 While
in synchronous communication clock is used to
synchronize data transmission between two devices.
Asynchronous Serial Interface cont..
4
 Asynchronous
 Transmittedand received data are not synchronized over any
extended period
 No synchronization between receiver and transmitter clocks
 Serial
 Usually character oriented
 Data stream divided into individual bits at the transmitter side
 Individual bits are grouped into characters at the receiving side
 Information is usually transmitted as ASCII-encoded characters
7 or 8 bits of information plus control bits
UART
 UART stand for Universal Asynchronous Receiver and Transmitter. UART can transfer
data bit by bit serially.
 There are other parallel communication protocols exists which are used to transfer
data in parallel mode like 8 bit at time. It can transfer only one bit at a time.
 By parallel communication data can be transferred with high speed. But speed come
with cost, it required as many wires as many bits user want to transfer at a time.
 Serial communication consists of only two wires, transmission wire and receive wire.
 Receiver wire is used to receive data sequentially from other UART device.
 Transmitter wire is used to send data sequentially to other UART microcontroller or
device.
UART
 Transmit or Tx pin of one UART device is directly connected with
receive or Rx pin of other device and vice versa.
 Other than these two pins ground pins of both devices should be
connected with each other.
 Now the question is How UART communication achieve
synchronization with clock signal?
 It achieves synchronization through baud rate and stat/stop bit.
 Baud rate defines how many bits a device can send or receive per
second. It is also know as the rate of data transfer in serial
communication. Baud rate can be 4800, 9600 etc.
 UART cont..
 Baud rate of both receiver and transmitting device should be same.
 Picture shows the structure of UART.
 Each frame consists of start bit. data bits, parity bit and stop bit
 When transmitter wants to send data to other device. It send start signal by
making a transition from high to low signal and receiver acknowledge this start
bit and start receiving data bit by bit. For example in above picture data is of 8
bits. By 8 bits mean by UART we can send only one character per frame.

• After completing data transfer, transmitter

sends stop signal to receiver by sending
digital high signal.
Asynchronous Serial Interface,
8
cont..
 MARK level (or OFF, or 1-state, or 1-level)
 This is also the idle state (before the transfer begins)
 SPACE level (or ON, or 0-state, or 0-level)
 One character:
 Start bit: space level
 Data bits
 Optional parity bit
 Optional stop bit
Asynchronous Serial Interface,
9
cont..
 12 possible basic formats:
7 or 8 bits of data
 Odd, even, or no parity
 1 or 2 stop bits
 Others exist also: no stop bits, 4/5/6 data bits,
1.5 stop bits, etc.
Least significant bit
RS-232 Interface Standard
10
 Bi-polar:
 +3 to +12V (ON, 0-state, or SPACE condition)
 -3 to –12V (OFF, 1-state, or MARK condition)
 Modern computers accept 0V as MARK
 “Dead area” between –3V and 3V is designed to absorb line
noise
 Originally developed as a standard for communication
between computer equipment and modems

TIA-232 line type and TTL voltage to/from

TIA-232 voltage
logic level MAX232
Data transmission
+3 V to +15 V 0V
(Rx/Tx) logic 0
Data transmission
−3 V to −15 V 5V
(Rx/Tx) logic 1
RS-232 Interface Standard
11

 Each manufacturer may choose to implement only a subset

of functions defined by this standard
 Two widely used connectors: DB-9 and DB-25
 Basic control signals
 RTS (Request to send):
DTE indicates to the DCE that it wants to send data
 CTS (Clear to send):
DCE indicates that it is ready to receive data
 DSR (Data set ready):
indication from the DCE (i.e., the modem) that it is on
 DTR (Data terminal ready):
indication from the DTE that it is on
RS-232 Interface Standard 12
 DB-25 connector is described in the book;
let’s take a look at DB-9
RS-232 Interface Standard
Example: 9 to 25 pin cable layout for asynchronous data 13

9-pin 25-pin
Description Signal Source DTE or DEC
DTE DCE

Carrier Detect CD 1 8 from Modem

Receive Data RD 2 3 from Modem

Transmit Data TD 3 2 from Terminal/Computer

Data Terminal Ready DTR 4 20 from Terminal/Computer

Signal Ground SG 5 7 from Modem

Data Set Ready DSR 6 6 from Modem

Request to Send RTS 7 4 from Terminal/Computer

Clear to Send CTS 8 5 from Modem

Ring Indicator RI 9 22 from Modem

PIC16F877A an example code for Serial communication
Serial Peripheral Interface
16
 Serial Peripheral Interface – SPI
 It is a synchronous serial data link standard named by
Motorola that operates in full duplex mode
 Devices communicate in master/slave mode where the master
device initiates the data frame. Multiple slave devices are
allowed with individual slave select (chip select) lines.
 The SPI bus specifies four logic signals.
 SCLK — Serial Clock (output from master)
 MOSI/SIMO — Master Output, Slave Input (output from master)
 MISO/SOMI — Master Input, Slave Output (output from slave)
 SS — Slave Select (active low; output from master)
SPI Mode: Signal Definition
17
 SIMO Slave in, master out
 Master mode: SIMO is the data output line.
 Slave mode: SIMO is the data input line.
 SOMI Slave out, master in
 Master mode: SOMI is the data input line.
 Slave mode: SOMI is the data output line.
 UCLK USART SPI clock
 Master mode: UCLK is an output.
 Slave mode: UCLK is an input.
 STE Slave transmit enable. Used in 4-pin mode to allow multiple masters on a single bus. Not
used in 3-pin mode.
 4-Pin master mode:
 When STE is high, SIMO and UCLK operate normally.
 When STE is low, SIMO and UCLK are set to the input direction.
 4-pin slave mode:
 When STE is high, RX/TX operation of the slave is disabled and SOMI is forced to the input direction.
 When STE is low, RX/TX operation of the slave is enabled and SOMI operates normally.