UNIT 5 Lecture-6

Electrical Science-2 (15B11EC211)
Unit-5
Clamper Circuit
Lecture-6
Outline
• Content
▫ Introduction to clampers
▫ Classifications
▫ Positive clampers
▫ Negative clampers
▫ Biased clampers
▫ Examples
▫ Summary of clampers
▫ Reference
Introduction of clampers
• A clamper is a network constructed of a
diode, a resistor, and a capacitor that
shifts a waveform to a different dc level
without changing the appearance of the
applied signal.
• In other words, the clamper circuit
moves the whole signal up or down to set
either the positive peak or negative peak
of the signal at the desired level.
• Clamping networks have a capacitor
connected directly from input to output
with a resistive element in parallel with
the output signal. The diode is also in
parallel with the output signal but may or
may not have a series dc supply as an
added element.
Ref 1
Classifications
• Negative clampers
• Positive clampers
• Biased clampers
Ref 1
Negative clamper
• The Negative Clamping circuit consists of a
diode connected in parallel with the load.
• The capacitor used in the clamping circuit can
be chosen such that it must charge very quickly
and it should not discharge very drastically. The
anode of the diode is connected to the capacitor
and cathode to the ground.
• This type of clamping circuit shifts the input
waveform in a negative direction, as a result the
waveform lies below a DC reference voltage
• During the positive half cycle (interval 0 to T/2) of the input,
the diode is in forward bias and as the diode conducts the
capacitor charges very quickly.
• For the positive half cycle the network will appear as shown
in Figure. The short-circuit equivalent for the diode will
result in V for this time interval.
• During this same interval of time, the time constant

determined by τ= RC is very small because the resistor R
has been effectively “shorted out” by the conducting diode
and the only resistance present is the inherent (contact,
wire) resistance of the network. The result is that the
capacitor will quickly charge to the peak value of V volts.
• During the negative half cycle (interval T/2 to T) of the input, the
diode will be in reverse bias and the diode will not conduct, the
output voltage will be equal to the sum of the applied input
voltage and the charge stored in the capacitor during reverse
bias. The output waveform is same as input waveform, but shifted
below 0 volts as shown in below figure.
• Applying Kirchhoff’s voltage law around the input loop results in,
Positive clampers
• The circuit of the positive clamper is similar to
the negative clamper but the direction of the
diode is inverted in such a way that the cathode
of the diode is connected to the capacitor.
• This type of clamping circuit shifts the input
waveform in a positive direction, as a result the
waveform lies above a DC reference voltage.
• A Clamping circuit restores the DC level. When
a negative peak of the signal is raised above to
the zero level, then the signal is said to be
positively clamped.
• During the positive half wave cycle diode goes off, output
voltage of the circuit will be the sum of applied input
voltage and the charge stored at capacitor.
• During the negative half wave cycle, the diode starts to

conduct and charges the capacitor very quickly to its
maximum value. The output waveform of the positive
clamper shifts towards the positive direction above the 0
volts as shown in below figure.
Biased clamper
• The additional dc supply connected within diode as shown
in figure.
• For the positive half cycle

• If , diode is OFF,
• If, diode is ON, and the capacitor charge up to voltage
• In this case the resistor R is not shorted out by the diode.
• For the negative half cycle,
• During the negative half cycle, the diode
is reverse biased by both input supply
voltage and battery voltage (V1).
• Output
Example 1
• Determine the output voltage of given
network
solution
• Here you can see, the frequency is 1000 Hz, resulting in a period of 1
ms and an interval of 0.5 ms between levels. The analysis will begin
with the period t1-t2 of the input signal since the diode is in its short-
circuit state. For this interval the network will appear as shown in Fig.
• The result is V0= 5 V for this interval.

• Applying Kirchhoff’s voltage law around the input loop
results in -20V+Vc-5V=0, Vc= 25V
• The capacitor will therefore charge up to 25 V. In this case
the resistor R is not shorted out by the diode.
• For the period t2 to t3 the network will appear as shown in Fig.
• The open-circuit equivalent for the diode removes the 5-V battery
from having any effect on Vo , and applying Kirchhoff’s voltage
law around the outside loop of the network results in
• +10 V+25 V – Vo=0
• V0=35 V
• The time constant for the discharging τ=RC=
• The total discharge time is therefore 5 τ = 5(10 ms) = 50 ms.
• Since the interval t2 - t3 will only last for 0.5 ms, it is certainly a
good approximation that the capacitor will hold its voltage during
the discharge period between pulses of the input signal. The
resulting output appears in Fig. with the input signal. You can
see the output swing of 30 V matches the input swing.
input output
Practice problem
• Repeat Example 1 using a silicon diode
with Vd 0.7 V.
Summary of clampers
References
• [1] R. Boylestad and L. Nashelsky, ‘Electronic
Devices and Circuit Theory’, PHI, 7e, 2001.

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Electrical Science-2 (15B11EC211)

• During this same interval of time, the time constant

• During the negative half wave cycle, the diode starts to

• For the positive half cycle

• The result is V0= 5 V for this interval.

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