HDL MODELS OF

C O M B I N AT I O N A L
CIRCUITS
 MODELING STYLES
The logic of a module can be described in any
one (or a combination) of the following
modeling styles:
• Structural or Gate-level modeling using
instantiations of predefined and user-defined
primitive gates.
• Dataflow modeling using continuous
assignment statements with the keyword
assign .
• Behavioral modeling using procedural
assignment statements with the keyword
always
 Description of Models
• Gate-level (structural) modeling describes a
circuit by specifying its gates and how they are
connected with each other.
• Dataflow modeling is used mostly for
describing the Boolean equations of
combinational logic.
• Behavioral modeling is used to describe
combinational and sequential circuits at a
higher level of abstraction.
Gate-Level Modeling
 Gate Level Modeling
• In this type of representation, a circuit is
specified by its logic gates and their
interconnections.
• Gatelevel modeling provides a textual
description of a schematic diagram.
• The Verilog HDL includes 12 basic gates as
predefined primitives.
• Four of these primitive gates are of the three-
state type.
• The other eight are listed as……….
 Primitives
• They are all declared with the lowercase
keywords and, nand, or, nor, xor, xnor, not,
and buf .
• Primitives such as and are n -input primitives.
• They can have any number of scalar inputs
(e.g., a three-input and primitive).
• The buf and not primitives are n -output
primitives.
• A single input can drive multiple output lines
distinguished by their identifiers.
 Vectors -Definition
• output [0: 3] D;
• wire [7: 0] SUM;
 Dataflow Modeling
• Verilog HDL provides about 30 different operators.
• It is necessary to distinguish between arithmetic and logic
operations, so different symbols are used for each.
• The plus symbol indicates the arithmetic operation of addition;
• the bitwise logic AND operation (conjunction) uses the symbol
&.
• There are special symbols for bitwise logical OR (disjunction),
NOT, and XOR.
• The equality symbol uses two equals signs (without spaces
between them) to distinguish it from the equals sign used with
the assign statement.
• The bitwise operators operate bit by bit on a pair of vector
operands to produce a vector result.
• The concatenation operator provides a mechanism for
appending multiple operands
 Features of Data Flow Modeling
• Dataflow modeling uses continuous assignments and the keyword assign.
• A continuous assignment is a statement that assigns a value to a net.
• The data type family net is used in Verilog HDL to represent a physical
connection between circuit elements.
• A net is declared explicitly by a net keyword (e.g., wire ) or by declaring
an identifier to be an input port.
• The logic value associated with a net is determined by what the net is
connected to.
• If the net is connected to an output of a gate, the net is said to be driven
by the gate, and the logic value of the net is determined by the logic
values of the inputs to the gate and the truth table of the gate.
• If the identifier of a net is the left-hand side of a continuous assignment
statement or a procedural assignment statement, the value assigned to
the net is specified by a Boolean expression that uses operands and
operators.
 Example Data Flow Modeling
• assign Y (A && S) || (B && S)
 Conditional Operator
Syntax:
assign OUT select ? A : B;
 Behavioral modeling
• Behavioral modeling represents digital circuits
at a functional and algorithmic level.
• It is used mostly to describe sequential
circuits, but can also be used to describe
combinational circuits
 Keywords in Behavioral Model
• Behavioral descriptions use the keyword always ,
followed by an optional event control expression and
a list of procedural assignment statements.
• The event control expression specifies when the
statements will execute.
• The target output of a procedural assignment
statement must be of the reg data type.
• Contrary to the wire data type, whereby the target
output of an assignment may be continuously
updated, a reg data type retains its value until a new
value is assigned.
 Binary Numbers in Verilog
• Binary numbers in Verilog are specified and interpreted with the letter b
preceded by a prime.
• The size of the number is written first and then its value.
• Thus, 2’b01 specifies a two-bit binary number whose value is 01.
• Numbers are stored as a bit pattern in memory, but they can be
referenced in decimal, octal, or hexadecimal formats with the letters d’,o’,
and h’, respectively.
• If the base of the number is not specified, its interpretation defaults to
decimal.
• If the size of the number is not specified, the system assumes that the
size of the number is at least 32 bits;
 Writing a Simple Test Bench
• A test bench is an HDL program used for describing
and applying a stimulus to an HDL model of a circuit
in order to test it and observe its response during
simulation.
• Test benches can be quite complex and lengthy and
may take longer to develop than the design that is
tested.
• The results of a test are only as good as the test
bench that is used to test a circuit.
• Care must be taken to write stimuli that will test a
circuit thoroughly, exercising all of the operating
features that are specified.
 Keyword : always
• always is a Verilog language construct
specifying how the associated statement is to
execute (subject to the event control
expression).
• The always statement executes repeatedly in
a loop
 Keyword:initial
• The initial statement executes only once,
starting from simulation time 0, and may
continue with any operations that are delayed
by a given number of time units, as specified
by the symbol #.
 Example:1
//Example
initial begin A 0;
B 0;
#10 A 1;
#20 A 0;
B 1;
end
 Example 2
initial
begin
D 3’b000;
repeat (7)
#10 D= D + 3’b001;
end
 Stimulus module
• A stimulus module has the following form:
module test_module_name;
// Declare local reg and wire identifiers.
// Instantiate the design module under test.
// Specify a stopwatch, using $finish to terminate
the simulation.
// Generate stimulus, using initial and always
statements.
// Display the output response (text or graphics (or
both)).
endmodule