COMPUTER

ORGANIZATION
&
ARCHITECTURE
 Unit-
3
Basic Computer
Organization & Design

2
 Basic Computer Organization
& Design 6. Memory-Reference
1. Instruction Instructions
Codes
7. Input-Output and
2. Computer Interrupt
Registers
8. Complete Computer
3. Computer Description
Instructions
9. Design of Basic
4. Timing and Computer
Control
10. Design of Accumulator3
5. Instruction Cycle Logic
nstruction Codes
Instruction Codes:

* The organization of the computer is defined by its internal registers, the timing and
control structure, and the set of instructions that it uses.

* Internal organization of a computer is defined by the sequence of micro-operations it

performs on data stored in its registers.

• Computer can be instructed about the specific sequence of operations it must

perform.
• User controls this process by means of a Program.

* Program: set of instructions that specify the operations, operands, and the sequence
by which processing has to occur.

* Instruction: a binary code that specifies a sequence of micro-operations for the 4

computer.
The computer reads each instruction from memory and places it in a control register.
The control then interprets the binary code of the instruction and proceeds to execute it
by issuing a sequence of micro-operations. – Instruction Cycle

Instruction Code: group of bits that instruct the computer to perform specific
operation.

Instruction code is usually divided into two parts: Opcode and address(operand)

5
nstruction Codes The Operation code
(Opcode) field
determines the process
that needs to be
performed The Address field
The Mode field specifies contains the operand's
how the operand locates location, i.e., register
or memory location.

15 14 12 11 0

Instruction 6
Format
Operation Code (opcode):

• Group of bits that define the operation

• Eg: add, subtract, multiply, shift, complement.

• No. of bits required for opcode depends on no. of operations available in computer.

• n bit opcode >= 2 n (or less) operations

• Address (operand):

• Specifies the location of operands (registers or memory words)

• Memory words are specified by their address

• Registers are specified by their k-bit binary code

• k-bit address >= 2 k registers

7
Stored Program Organization:

• The ability to store and execute instructions is the most important property of a general-purpose computer.
That type of stored program concept is called stored program organization.

• The simplest way to organize a computer is to have one processor register and an instruction code format
with two parts. The first part specifies the operation to be performed and the second specifies an address.

8
* Instructions are stored in one section of memory and data in another.

• For a memory unit with 4096 words we need 12 bits to specify an address since 212 = 4096.

• If we store each instruction code in one 16-bit memory word, we have available four bits for
the operation code (abbreviated opcode) to specify one out of 16 possible operations, and 12
bits to specify the address of an operand.

• Accumulator (AC):

• Computers that have a single-processor register usually assign to it the name accumulator
and label it AC.

• The operation is performed with the memory operand and the content of AC.

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Addressing of Operand

Addressing of Operand:

10
Computer Registers

Computer Registers:

What is the need for computer registers?

• The need of the registers in computer for Instruction sequencing needs a counter to
calculate the address of the next instruction after execution of the current instruction is
completed (PC).

• Necessary to provide a register in the control unit for storing the instruction code after it is
read from memory (IR).

• Needs processor registers for manipulating data (AC and TR) and a register for holding a
memory address (AR).

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12
 S2

COMMON BUS
S1 Bus

Common Bus System S0 S2 S 1 S 0 Register

0 0 0 x
SYSTEM
Memory unit 7
4096 x 16
Address 0 0 1 AR
Write Read 0 1 0 PC
AR 1
0 1 1 DR
1 0 0 AC
LD INR CLR
1 0 1 IR
PC 2 1 1 0 TR
LD INR CLR 1 1 1 Memory
DR 3

LD INR CLR

E
ALU AC 4

LD INR CLR

INPR

IR 5

LD

TR 6

LD INR CLR

OUTR
Clock
LD
16-bit common bus
 Instructions are of
three types
• Register reference
12 bits to specify an instructions
address • Memory reference
instructions
Addressing
• IO reference instruction
mode

I = 0 : direct
addressing

I = 1 : indirect
addressing

14
15
Timing and Control Timing and Control

The timing for all registers in the basic computer is controlled by a master clock
generator.

The clock pulses are applied to all flip-flops and registers in the system, including the
flip-flops and registers in the control unit.

The clock pulses do not change the state of a register unless the register is enabled by
a control signal.

The control signals are generated in the control unit and provide control inputs for the
multiplexers in the common bus, control inputs in processor registers, and micro
operations for the accumulator.

There are two major types of control organization: o Hardwired control o Micro
programmed control 16
17
18
19
20
Instruction Cycle Instruction Cycle
• Every program is a collection of instructions
• Each instruction of the program is executed using instruction cycle.
In Basic Computer, a machine instruction is executed in the following cycle:
1. Fetch an instruction from memory (Retrieving Instruction from the
memory)
2. Decode the instruction (which operation the corresponding instruction
will perform)
3. Read the effective address from memory if the instruction has an indirect
address
4. Execute the instruction

Fetch Next Execute HALT

START
Instruction Instruction
21
22
Fetch and Decode

Initially, the program counter PC is loaded with the address of the first instruction in the program

The sequence counter SC is cleared to 0, providing a decoded timing signal T0

The micro operations for the fetch and decode phases can be specified by the following register transfer
statements

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24
 MEMORY REFERENCE INSTRUCTIONS
Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
• The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, or
during timing signal T3 when I = 1

• Memory cycle is assumed to be short enough to complete in a CPU cycle

• The execution of MR instruction starts with T4

AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC

ADD to AC
D1T4: DR  M[AR] Read operand 25
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0

STA: Store AC
D3T4: M[AR]  AC, SC  0

BUN: Branch Unconditionally

D4T4: PC  AR, SC  0

BSA: Branch and Save Return Address

M[AR]  PC, PC  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0 26
 FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
Memory-reference instruction

AND ADD LDA STA

D T 4 D 1T 4 D 2T 4 D 3T 4
0
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D 0T 5 D 1T 5 D 2T 5

AC  AC DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D 4T 4 D 5T 4 D 6T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D 5T 5 D 6T 5
PC  AR DR  DR + 1
SC  0
D 6T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1) 27
SC  0
Input-Output and Interrupt Input-Output and Interrupt

Instructions and data stored in memory must come from some input device.

Computational results must be transmitted to the user through some output

device

To demonstrate the most basic requirements for input and output communication, we
will use as an illustration a terminal unit with a keyboard and printer

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Input-Output Configuration

29
Input-Output Instructions

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 FLOWCHART FOR INTERRUPT CYCLE

R = Interrupt flip-flop

=0 Interrupt cycle
Instruction cycle =1
R

Store return address

Fetch and decode
in location 0
instructions
M[0]  PC

=0
Execute IEN
instructions =1 Branch to location 1
PC  1
=1
FGI

=0

=1 IEN  0
FGO R0

=0

R1

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Interrupt cycle Interrupt cycle Memory
Before interrupt After interrupt cycle

0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120

Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program

Register Transfer Statements for Interrupt Cycle 1 BUN 0 1 BUN 0

• R F/F  1 if IEN (FGI + FGO)T0T1T2

 T0T1T2 (IEN)(FGI + FGO): R  1

• The fetch and decode phases of the instruction cycle

must be modified  Replace T0, T1, T2 with R'T0, R'T1, R’T2

• The interrupt cycle :

RT0: AR  0, TR  PC
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RT1: M[AR]  TR, PC  0
COMPLETE COMPUTER DESCRIPTION
Flowchart of Operations

start
SC  0, IEN  0, R  0

=0(Instruction Cycle) =1(Interrupt Cycle)

R
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

=1(Register or I/O) =0(Memory Ref)

D7

=1 (I/O) =0 (Register) =1(Indir) =0(Dir)

I I

D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction
33
 DESIGN OF BASIC COMPUTER(BC)

Hardware Components of BC
• A memory unit : 4096 x 16.

• Registers: Flip-
Flops(Status):

AR, PC, (12 bit) I, S, E, R, IEN, FGI, and FGO

DR, AC, IR, TR, (16 bit)
OUTR, INPR, (8 bit) and
SC (4 bit)

• Decoders: 1) 3x8 Opcode decoder 2) 4x16 timing decoder

• Common bus: 16 bits

• Control logic gates: Adder and Logic circuit: Connected to AC

 Input Controls of the nine registers
 Read and Write Controls of memory
 Set, Clear, or Complement Controls of the flip-flops
 S2, S1, S0 Controls to select a register for the bus
 AC, and Adder and Logic circuit 34
 COMPLETE COMPUTER DESCRIPTION
Microoperations

Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect AR  M[AR]
D7IT3:
Interrupt
T0T1T2(IEN)(FGI + FGO): R1
AR  0, TR  PC
RT0: M[AR]  TR, PC  0
RT1: PC  PC + 1, IEN  0, R  0, SC  0
Memory-Reference RT2:
AND DR  M[AR]
D0T4: AC  AC  DR, SC  0
ADD D0T5: DR  M[AR]
D1T4: AC  AC + DR, E  Cout, SC  0
LDA D1T5: DR  M[AR]
D2T4: AC  DR, SC  0
STA M[AR]  AC, SC  0
BUN D2T5: PC  AR, SC  0
BSA D3T4: M[AR]  PC, AR  AR + 1
D4T4: PC  AR, SC  0
ISZ D5T4: DR  M[AR]
D5T5: DR  DR + 1
D6T4: M[AR]  DR, if(DR=0) then (PC  PC + 1),
D6T5: SC  0
D6T6:
35
Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA AC  0
rB11:
CLE E0
CMA rB10:
AC  AC
CME rB9: E  E
CIR rB8: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB7: AC  shl AC, AC(0)  E, E  AC(15)
INC rB6: AC  AC + 1
SPA rB5: If(AC(15) =0) then (PC  PC + 1)
SNA rB4: If(AC(15) =1) then (PC  PC + 1)
SZA If(AC = 0) then (PC  PC + 1)
SZE rB3:
If(E=0) then (PC  PC + 1)
HLT rB2: S0
rB1:
Input-Output rB0: (Common to all input-output instructions)
(i = 6,7,8,9,10,11)
D7IT3 = p SC  0
INP IR(i) = Bi AC(0-7)  INPR, FGI  0
OUT p: OUTR  AC(0-7), FGO  0
SKI pB11: If(FGI=1) then (PC  PC + 1)
SKO If(FGO=1) then (PC  PC + 1)
pB10:
ION IEN  1
IOF pB9: IEN  0
pB8:
pB7:
pB6:
36
 CONTROL OF REGISTERS AND MEMORY

Address Register; AR
Scan all of the register transfer statements that change the content of AR:

12 12
From bus To bus
R’T0: AR  PC LD(AR) D' AR
7
R’T2: AR  IR(0-11) LD(AR)
I
D’7IT3: AR  M[AR] LD(AR) LD Clock
RT0: AR  0 CLR(AR) T
3
T INR
D5T4: AR  AR + 1 INR(AR) 2
CLR

T0
LD(AR) = R'T0 + R'T2 + D'7IT3
D
CLR(AR) = RT0
T4

INR(AR) = D5T4

37
 CONTROL OF FLAGS
IEN: Interrupt Enable Flag

pB7: IEN <- 1 (I/O Instruction)

pB6: IEN <- 0 (I/O Instruction)
RT2: IEN <- 0 (Interrupt)

p = D7IT3 (Input/Output Instruction)

D
7
p
I
J Q IEN
B
7
T3

B
6
K

R
T
2

38
 CONTROL OF COMMON BUS

x1
x2 S2
Multiplexer
x3
Encoder S1 bus select
x4
x5 inputs
x6 S0
x7

selected
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory

For AR
D4T4: PC <- AR
D5T5: PC <- AR

x1 = D4T4 + D5T5 39
 DESIGN OF ACCUMULATOR LOGIC
16

Adder and
Circuits associated with AC 16 16 16
From DR logic AC

circuit To bus
8
From INPR

LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC <- AC  DR AND with DR
D1T5: AC <- AC + DR Add with DR
D2T5: AC <- DR Transfer from DR
pB11: AC(0-7) <- INPR Transfer from INPR
rB9: AC <- AC Complement
rB7 : AC <- shr AC, AC(15) <- E Shift right
rB6 : AC <- shl AC, AC(0) <- E Shift left
rB11 : AC <- 0 Clear
rB5 : AC <- AC + 1 Increment 40