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Readd TIM21/TIM22 to l0xx series #659

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Merged
merged 3 commits into from
Dec 22, 2021
Merged

Readd TIM21/TIM22 to l0xx series #659

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fa959e1
Add entire TIM21/TIM22 config into l0xx
jamwaffles Nov 14, 2021
639fcd5
Remove copypasta, use tim21.yaml directly
jamwaffles Dec 8, 2021
f7e638c
Add TI2_RMP back in
jamwaffles Dec 14, 2021
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10 changes: 6 additions & 4 deletions peripherals/tim/tim21.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,6 @@

"TIM2?":
CR1:
CKD:
Div1: [0, "t_DTS = t_CK_INT"]
Div2: [1, "t_DTS = 2 × t_CK_INT"]
Div4: [2, "t_DTS = 4 × t_CK_INT"]
Comment on lines -5 to -8
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As mentioned in the commit comment, this is already present in tim_basic.yaml. tim21.yaml is only used in tim_l0 currently so I don't think this should cause any issues.

CMS:
EdgeAligned: [0, "The counter counts up or down depending on the direction bit"]
CenterAligned1: [1, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
Expand Down Expand Up @@ -162,3 +158,9 @@
COMP1_OUT: [2, "TIM2x ETR input connected to COMP1_OUT"]
LSE: [3, "TIM2x ETR input connected to LSE clock"]

# TI2_RMP is only available on TIM21
TIM21:
OR:
TI2_RMP:
GPIO: [0, "TIM2x TI2 input connected to GPIO"]
COMP2_OUT: [1, "TIM2x TI2 input connected to COMP2_OUT"]
7 changes: 2 additions & 5 deletions peripherals/tim/tim_l0.yaml
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Expand Up @@ -30,8 +30,5 @@
LSE: [5, "TIM2 ETR input is connected to LSE"]
HSI: [3, "TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set"]

"TIM21":
OR:
TI2_RMP:
GPIO: [0, "TIM2x TI2 input connected to GPIO"]
COMP2_OUT: [1, "TIM2x TI2 input connected to COMP2_OUT"]
_include:
- ./tim21.yaml
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