A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.
LLM-Aided FPGA Design for Signal Processing Applications
DaCH: dataflow cache for high-level synthesis.
Advanced multi-band GNSS SDR front-end implementation in an RFSoC integrated circuit. GPL-3.0 license
LLM-Aided FPGA Design Optimization
FPGA Acceleration for the LoFreq variant caller
Mixing HLS and Backend Versions in Vitis
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
Vitis (Vivado) HLS Examples
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
Work on your Vitis HLS project from within VS Code
An accelerated implementation of the kNN algorithm on the Kria KV260 FPGA
Xilinx Tools Tutorials
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
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