VHDL Project: Title: "Stop Watch"

VHDL PROJECT
TITLE : “STOP WATCH”
PREPARED BY:-
07EC220:Trivedi Umang
07EC235:Soriya Hitesh
07EC244:Patel Bhavesh
GUIDED BY:-
Mr.RUTVIJ JOSHI
Program:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY stop IS
PORT (clk, rst,stop : IN STD_LOGIC;
digit1: OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
e ,f:inout std_logic;
seg : inout std_logic_vector(3 downto 0));
END stop;
ARCHITECTURE watch OF stop IS

BEGIN
process(clk)
variable count:integer range 1 to 250;
begin
if clk'event and clk='1' then
if count = 250 then
e <= not(e);
count:= 1;
else
count:= count +1;
end if;
end if;
end process;
process(e)
variable count1:integer range 1 to 2499750;
begin
if clk'event and clk='1' then
if count1 = 2499750 then
f <= not(f);
count1:= 1;
else
count1:= count1 +1;
end if;
end if;
end process;
process(e)
variable count2: integer range 0 to 3;
begin
if e'event and e = '1' then
if count2 = 0 then
seg <= "1110";
count2 := count2 + 1;
elsif count2 = 1 then
seg <= "1101";
seg <= "1011";
seg <= "0111";
count2 := 0;
end if;
end if;
end process;
process(rst,stop,f)
variable temp1:integer range 0 to 10;
begin
if(rst='1')then
temp1:=0;
temp2:=0;
temp3:=0;
temp4:=0;
elsif(stop='1')then
null;
elsif(f'event and f='1')then

temp1:=temp1+1;
if(temp1=10)then
temp2:=temp2+1;
temp1:=0;
if(temp2=10)then
temp3:=temp3+1;
temp2:=0;
if(temp3=6)then
temp4:=temp4+1;
temp3:=0;
if(temp4=10)then
temp4:=0;
end if;
end if;
end if;
end if;
end if;
----conversion from BCD to SSD: --------
if temp1 = 0 and seg = "1110" then
digit1 <= "0000001";
elsif temp1 = 1 and seg = "1110" then
digit1 <= "1001111";
digit1 <= "0010010";
digit1 <= "0000110";
digit1 <= "1001100";
digit1 <= "0100100";
digit1 <= "0100000";
digit1 <= "0001111";
digit1 <= "0000000";
digit1 <= "0000100";
elsif temp2= 0 and seg = "1101" then

digit1 <= "0000001";
digit1 <= "1001111";
digit1 <= "0010010";
digit1 <= "0000110";
digit1 <= "1001100";
digit1 <= "0100100";
digit1 <= "0100000";
digit1 <= "0001111";
digit1 <= "0000000";
digit1 <= "0000100";

digit1 <= "0000001";
digit1 <= "1001111";
digit1 <= "0010010";
digit1 <= "0000110";
digit1 <= "1001100";
digit1 <= "0100100";

digit1 <= "0000001";
digit1 <= "1001111";
digit1 <= "0010010";
digit1 <= "0000110";
digit1 <= "1001100";
digit1 <= "0100100";
digit1 <= "0100000";
digit1 <= "0001111";
digit1 <= "0000000";
digit1 <= "0000100";
END IF;
END PROCESS;
END watch;
Explanation of the program:-

The program is VHDL code for “stop watch”. The
program enables to stop the watch when required
,and it is reset enable.On reset the three ssd get set to
zero and on stop , the corresponding value is
displayed on the ssd.
In the entity,the ports are selected according

To the requirements.The in ports are rst,clk and
stop.The inout ports are e,f and seg and the out port
is digit1.
In the architecture , four process are defined which

are executed concurrently.In each process the
statements are executed sequentially. In first process
the clock of the chip which is 50Mhz is divided such
that we get the time delay of 10 micro seconds.The
corresponding frequency is e.
In the second process the frequency of the crystal is

further divided into f which gives a time delay of 0.01
second. Which is corresponding to the 100th part of
the second which will be displayed in the rightmost
ssd.
In the third process the frequency e is selected and

taking into consideration the value of the value of
count2,the corresponding ssd is selected.
In the fourth process rst,stop and f are included in the
sensitivity list and temp1 , temp2 , temp3 , temp4 are
selected as variables .The variables are utilized to
reset the stop watch.If stop is equal to 1,due to the
“null” operation ,the current value will be displayed
continuously .If reset is equal to one, the values of
temp1,temp2,temp3,temp4 is set to 0.If neither stop
or reset is one ,than according to the values of temp
variables and the ssd selection values,the
corresponding value of the stop watch is displayed on
the ssd selected .The integer range of the temp1
variable is 0 to 10 because it resembles the seconds
value , the integer range of the temp2 variable is
selected to be 0 to 10 because it represents 10th part
of second. For temp3 the integer range is selected to
be 0 to 6 because 60 seconds make one minute and
for temp4 integer range 0 to 10 is selected for
minutes.
SCHEMATIC DIAGRAM:-
APPLICATION:-
 The stop watch is utilized to determine
time taken for accomplishment of
various purposes like in sports.
 The circuit can be utilized commercially
as stop watch.

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VHDL PROJECT

TITLE : “STOP WATCH”

ARCHITECTURE watch OF stop IS

elsif(f'event and f='1')then

elsif temp2= 0 and seg = "1101" then

elsif temp3= 0 and seg = "1011" then

elsif temp4= 0 and seg = "0111" then

Explanation of the program:-

In the entity,the ports are selected according

In the architecture , four process are defined which

In the second process the frequency of the crystal is

In the third process the frequency e is selected and

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