ERROR DETECTION & CORRECTION

“DATA NETWORKS” FOR JTOs PH-II – Error detection & Correction Techniques

ERROR DETECTION & CORRECTION TECHNIQUES

Transmission of bits as electrical signals suffers from many impairments which
ultimately result in introduction of errors in the bit stream. Digital systems are very
sensitive to errors and may malfunction of error rate is above a certain level.
Therefore, error control mechanisms are built into almost all digital systems. In this
module we will discuss some common error detection and correction mechanisms. We
begin with basic concept and terminology of coding theory, parity checking,
checksum and cyclic redundancy check methods of error detection are examined in
some detail. We then proceed to error correction methods which include block codes,
the Hamming code and convolution code. Mechanisms for error control in data
communication are based on detection of errors in a message and its retransmission.

TRANSMISSION ERRORS

Errors are introduced in the data bits during their transmission. These errors can be
categorized as: content errors, and flow integrity errors.

Content errors are errors in the content of a message, e.g., a “ 1” may be received as a
“0”. Such errors creep in due to impairment of the electrical signal in the transmission
medium.

Flow integrity errors refer to missing blocks of data. For example, a data block may
be lost in the network due to its having been delivered to a wrong destination.
In voice communication the listener can tolerate a good deal of signal distortion and
make sense of the received signal but digital systems are very sensitive to errors.
Measures are, therefore, built into a data communication system to counteract the
effect of errors. These measures include the following:

• Introduction of additional check bits in the data bits to detect content errors
• Correction of the errors
• Establishment of procedures of data exchange which enable detection of missing
blocks of date
• Recovery of the corrupted messages.

CODING FOR ERROR DETECTION AND CORRECTION

For error detection and correction, we need to add some check bits to a block of data
bits. The check bits are also called redundant bits because they do not carry any user
information. Check bits are so chosen that the resulting bit sequence has a unique
“characteristic” which enables error detection. Coding is the process of adding the
check bits.

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Some of the terms relating to coding theory are explained below:

• The block of data bits to which check bits are added is called a data word.
• The bigger block containing check bits is called the code word.
• Hamming distance or simply distance between two code words is the number of
disagreements between them. For example, the distance between the two words
given below is 3 (Fig. 1).
• The weight of a code word is the number of “1” s in the code word e.g., 11001100
has a weight of 4.
• A code set consists of all valid code words. As the valid code words have a built in
“characteristic” of the code set.

1 1 0 1 0 1 0 0
Distance =3

0 1 0 1 1 1 1 0

Fig. 1 Hamming distance.

Error detection

When a code word is transmitted, one or more of its bits may be reversed due to
signal impairment. The receiver can detect these errors if the received code word is
not one of the valid code words of the code set.

When errors occur, the distance between the transmitted and received code words
becomes equal to the number of erroneous bits (Fig.2).

Transmitted Received Number of Distance

Code Word Code Word Errors
11001100 11001110 1 1
10010010 00011010 2 2
10101010 10100100 3 3

Fig. 2 Hamming distance between transmitted and received code words.

In other words, the valid code words must be separated by a distance of more than 1
otherwise, even a single bit error will generate another valid code word and the error
will not be detected. The number of errors which can be detected depends on the
distance between any two valid code words. For example, if the valid code words are
separated by a distance of 4, up to three errors in a code word can be detected. By
adding a certain number of check bits and properly choosing the algorithm for
generating them, we ensure some minimum distance between any two valid code
words of a code set.

Error Correction
After an error is detected, there are two approaches to correction of errors:
1. Reverse Error Correction (REC)

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2. Forward Error Correction (FEC)

In the first approach, the receiver requests for retransmission of the code word
whenever it detects an error. In the second approach, the code set is so designed that it
is possible for the receiver to detect and correct the errors as well. The receiver locates
the errors by analyzing the received code word and reverse the erroneous bits.

An alternative way of forward error correction is to search for the most likely correct
code word. When an error is detected, the distances of all the valid code words from
the received invalid code word are measured. The nearest valid code word is the most
likely correct version of the received word (Fig. 3).

Valid Code Word Valid Code Word

10001110 10100110

3 Received Word 1

10110110

Valid Code Word 7 5 Valid Code Word

01001000 01011111

Fig.3 Error correction between valid based on the least Hamming distance.

If the minimum distance between valid code words is D, upto D/2 – 1 errors can be
corrected. More than D/2 – 1 errors will cause the received code word to be nearer to
the wrong valid code word.

Bit Error Rate (BER)

In analog transmission, signal quality is specified in terms of signal-to-noise ratio

(S/N) which is usually expressed in decibels. In digital transmission, the quality of
received digital signal is expressed in terms of Bit Error Rate (BER) which is the
number of errors in a fixed number of transmitted bits. A typical error rate on a high
quality leased telephone line is as low as 1 error in 106 bits or simply 1 × 10-6

ERROR DETECTION METHODS

Some of the popular error detection methods are:

• Parity checking
• Checksum error detection
• Cyclic Redundancy Check (CRC).
Each of the above methods has its advantages and limitations as we shall see in the
following section.

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Parity Checking

In parity checking methods, an additional bit called a “parity” bit is added to each data
word. The additional bit is so chosen that the weight of the code word so formed is
either even (even parity) or odd (odd parity) (Fig .4). All the code words of a code set
have the same parity (either odd or even) which is decided in advance.

Even Parity Odd Parity

P Data Word P Data Word

0 1001011 1 1001011
1 0010110 0 0010110

Fig. 4 Even and odd parity bits.

When a single error or an odd number of errors occurs during transmission, the parity
of the code word changes (Fig.5). Parity of the code word is checked at the receiving
end and violation of the parity rule indicates errors somewhere in the code word.
Transmitted Code 10010110 Even Parity
Received Code (single error) 00010110 Odd Parity (Error is detected)
Received Code (Double error) 00011110 Even Parity (Error is not
detected)
Fig. 5 Error detection by change in parity.

Note that double or any even number of errors will go undetected because the
resulting parity of the code word will not change. Thus, a simple parity checking
method has its limitations. It is not suitable for multiple errors. To keep the possibility
of occurrence of multiple errors low, the size of the data word is usually restricted to a
single byte.

Parity checking does not reveal the location of the erroneous bit. Also, the
received code word with an error is always at equal distance from two valid code
words. Therefore, errors cannot be corrected by the parity checking method.

EXAMPLE 2
Write the ASCII code of the word “ HELLO” using even parity.
Solution
Bit Positions 87654321
H 01001000
E 11000101
L 11001100
L 11001100
O 11001111
Burst Errors

There is a strong tendency for the errors to occur in bursts. An electrical interference
like lightning lasts for several bit times and, therefore, it corrupts a block of several
bits. The parity checking method fails completely in such situations. Checksum and
cyclic redundancy check are the two methods which can take care of burst errors.

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Checksum Error Detection

In checksum error detection method, a checksum is transmitted along with every

block of data bytes. Eight-bit bytes of a block of data are added in an eight-bit
accumulator. Checksum is the resulting sum in the accumulator. Being an eight-bit
accumulator, the carries of the most significant bits are ignored.

EXAMPLE 3

Find the checksum of the following message. The MSB is on the left-hand side of
each byte.
10100101 001001110 11100010 01010101 10101010 11001100 00100100

Solution
1 1 1 Carries
1 1 1 1 1 1
1 0 1 0 0 1 0 1
0 0 1 0 0 1 1 0
1 1 1 0 0 0 1 0
0 1 0 1 0 1 0 1 Data Bytes
1 0 1 0 1 0 1 0
1 1 0 0 1 1 0 0
0 0 1 0 0 1 0 0
1 0 0 1 1 1 0 0 Checksum Byte

After transmitting the data bytes, the checksum is also transmitted. The checksum is
regenerated at the receiving end and errors show up as a different checksum. Further
simplification is possible by transmitting the 2’ s complement of the checksum in
place of the checksum itself. The receiver in this case accumulates all the bytes
including the 2’s complement of the checksum. If there is no error, the contents of
the accumulator should be zero after accumulation of the 2’s complement of the
checksum byte.

The advantage of this approach over simple parity checking is that 8-bit addition
“mixes up” bits and the checksum is representative of the overall block. Unlike simple
parity where even number of errors may not be detected, in checksum there is 255 to
1 chance of detecting random errors.

Cyclic Redundancy Check

Cyclic Redundancy Check (CRC) codes are very powerful and are now almost
universally employed. These codes provide a better measure of protection at the lower
level of redundancy and can be fairly easily implemented using shift registers or
software.
A CRC code word of length N with m-bit data word is referred to as (N,m) cyclic
code and contains (N-m) check bits. These check bits are generated by modulo-2
division. The dividend is the data word followed by n= N-m zeros and the divisor is a
special binary word of length n+1. The CRC code word is formed by modulo-2
addition of the remainder so obtained and the dividend.

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EXAMPLE 6
Generate CRC code for the data word 110101010 using the divisor 10101.
Solution
Data Word 110101010
Divisor 10101
111000111 Quotient
1 0 1 0 1) 1101010100000 Dividend
10101
11111
10101
10100
10101
11000
10101
11010
10101
11110
10101
1011 Remainder
1101010100000
1011
Code Word1 1 0 1 0 1 0 1 0 1 0 1 1
In the above example, note that the CRC code word consists of the date word
followed by the remainder. The code word so generated is completely divisible by the
divisor because it is the difference of the dividend and the remainder (Modulo-2
addition and subtraction are equivalent). Thus, when the code word is again divided
by the same divisor at the receiving end, a non-zero remainder after so dividing will
indicate errors in transmission of the code word.
EXAMPLE 7
The code word of Example 6 be received as 1100100101011. Check if there are errors
in the code word.
Solution
Dividing the code word by 10101, we get
111110001
10101) 1100100101011
10101
11000
10101
1jhkhhkhkhhkj
11010
10101
11111
10101
10100
10101
11011
10101
1110 Remainder

Non-zero remainder indicates that there are errors in the received code word.

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Algebraic Representation of Binary Code Words

For the purpose of analysis, the binary codes are represented using algebraic
polynomials. In a polynomial of variable x, coefficients of the powers of x are the bits
of the code, the most significant bit being the coefficient of the highest power of x. the
data word of Example 6 can be represented by a polynomial M (x) as::

M(x) = 1x8 + 1x7 + 0x6 + 1x5 + 0x4 + 1x3 + 0x2 + 1x1 + 0x0
Or M(x) = x8 + x7 + x5 + x3 + x

The polynomial corresponding to the divisor is called the generating polynomial G(x)
. G(x) corresponding to divisor used in last example would be
G (x) = 1x4 + 0x3 + 1x2 + 0x1 + 1x0
Or G(x) = x4 + x2 + 1

The polynomial D(x) corresponding to the dividend (1101010100000) is

D(x) = x12 + x11 + x9 + x7 + x5 = x4. M(x)

If Q (x) is the quotient and R(x) is the remainder when D(x) is divided by G(x),

D(x) = Q(x). G(x) + R(x)

D(x) + R (x) = Q(x). G(x) + R(x) + R(x)
D(x) + R(x) = Q(x). G(x)

Thus, the CRC code D(x) +R(x) is completely divisible by G(x). This characteristic of
the code is used for detecting errors.
Some of the common generating polynomials and their applications are :

• CCITT V.41 x16 +x12+ x5 +1

It is used in HDLC/SDLC/ADCCP protocols.

• CRC –12 x12 + x11 + x3 + x2 +x 1
It is employed in BISYNC protocol with 6-bit characters.

• CRC-16 x16 +x15 +x2 + 1

It is used in BISYNC protocol with 8-bit characters.

• CRC-32 x32 +x26 +x23 +x22 +x16 +x12 +x11 +x10 +x8 +x7 +x5 +x4 +x2 +x +1
It is used with 8-bit characters when very high probability of error detection is
required.

FORWARD ERROR CORRECTION METHODS

To locate and correct errors require a bigger overhead in terms of number of check
bits in the code word. Some of the important error-correction codes which find
application in data transmission devices are:
• Block parity
• Hamming code
• Convolutional code.

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Block Parity

The concept of parity checking can be extended to detect and correct single errors.
The data block is arranged in a rectangular matrix form as shown in Fig.8 and two
sets of parity bits are generated, namely,
1. Longitudinal Redundancy Check (LRC)

2. Vertical Redundancy Check (VRC).

VRC is the parity bit associated with the character code and LRC is generated over
the rows of bits. LRC is appended to the end of data block. The bit 8 of the LRC
represents the VRC of the other 7 bits of the LRC. In Fig.6, even parity is used for the
LRC and the VRC.

COMPUTER
1 1 1 1 0 1 0 1 0 1
2 1 1 0 0 0 0 0 1 1
7-Bit 3 0 1 1 0 1 1 1 0 1
ASCII 4 0 1 1 0 0 0 0 0 0
Codes 5 0 0 0 1 1 1 0 1 0
6 0 0 0 0 0 0 0 0 0
7 1 1 1 1 1 1 1 1 0
1 1 0 0 0 1 1 1 1

Even Parity Even Parity

Bits (VRC) Bits (LRC)

Fig.6 Vertical and longitudinal parity check bits.

Bit Transmission Sequence

11000011 11110011 10110010 00001010 10101010 00101011 10100011
01001011 11100001

Even a single error in any bit results in failure of longitudinal redundancy check in
one of the rows and vertical redundancy check in one of the columns. The bit which is
common to the row and column is the bit in error.

Multiple errors in rows and columns can be detected but cannot be corrected as the
bits which are in error cannot be located.

EXAMPLE 8

The following bit stream is encoded using VRC, LRC and even parity. Correct the
error, if any.
11000011 11110011 10110010 00001010 10111010 00101011 10100011
01001011 11100001

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“DATA NETWORKS” FOR JTOs PH-II – Error detection & Correction Techniques

Solution
1 1 1 0 1 0 1 0 1
1 1 0 0 0 0 0 1 1
0 1 1 0 1 1 1 0 1
1
0 1 1 0 1 0 0 0 0 Wrong Parity

0 0 0 1 1 1 0 1 0
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 0
1 1 0 0 0 1 1 1 1

Wrong Parity
Fourth bit of the fifth byte is in error. It should be “0”.

Hamming Code

It is the single error correcting code devised by Hamming. In this code, there are
multiple parity bits in a code word. Bit positions 1, 2, 4, 8... etc. Of the code word are
reserved for the parity bits. The other bit position are for the data bits (Fig. 7). The
number of parity bits required for

1 2 3 4 5 6 7 8 9 10 11
P1 P2 D P4 D D D P8 D D D

P: Parity Bit D: Data Bit

Fig. 7 Location of parity bits in Hamming code.

Correcting single bit errors depends on the length of the code word. A code word of
length n contains m parity bits, where m is the smallest integer satisfying the
condition:

2m ≥ n + 1
The MSB of the data word is on the right-hand side and its position is third in Fig. 7.
As usual, the LSB is transmitted first.

Each data bit is checked by a number of parity bits. Data bit position expressed as
sum of the powers of 2 determines parity bit positions which check the data bit. For
example, a data bit in position 6 is checked by parity bits P4 and P2 (6=22 + 21 ).
Similarly, data bit in position 11 is checked by parity bits P8, P2and P1 (11=23 + 21
+20). Table 1 gives the parity bit position which check the various data bit positions.

Each parity bit is determined by the data bits it checks. Even or add parity can be
used. For

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Table 1 Data Bit Position Checked by the Parity Bits

Data bit Parity bit positions

Positions P1 P2 P4 P8
3 × ×
5 × ×
6 × ×
7 × × ×
9 × ×
10 × ×
11 × × ×
12 × ×

example, if even parity is used, P2 is such that the number of “1” s in 2nd, 3rd, 6th,
7th, 10th and 11th positions is even. The logic behind this way of generating the
parity bits is that when a code word suffers an error, all the parity bits which check the
erroneous bit will indicate violation of the parity rule and the sum of these parity bit
positions will indicate the position of the erroneous bit. For example, if the 11th bit is
in error, parity bits P8, P2 and P1 will indicate error and 8+2+1=11 will immediately
point to the 11th bit.

EXAMPLE 9

Generate the code word for ASCII character “K”= 1001011. Assume even parity for
the Hamming code. No character parity is used.

Solution

Bit positions

1 2 3 4 5 6 7 8 9 10 11
P1 P2 1 P4 0 0 1 P8 0 1 1

First parity bit P1 1 0 1 0 1 P1=1

Second parity bit P2 1 0 1 1 1 P2=0
Third parity bit P4 0 0 1 P4=1
Fourth parity bit P8 0 1 1 P8=0

Code Word 1 0 1 1 0 0 1 0 0 1 1

EXAMPLE 10

Detect and correct the single error in the received Hamming code word 10110010111.
Assume even parity.

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Solution

Bit positions Parity

Check
1 2 3 4 5 6 7 8 9 10 11
P1 P2 D P4 D D D P8 D D D

Code word 1 0 1 1 0 0 1 0 1 1 1
First Check 1 1 0 1 1 1 Odd fail
1
(P1, 3,5,7,9,11)
Second check 0 1 0 1 1 1 Even Pass
(P2, 3,6,7,10,11)
Third check 1 0 0 1 Even Pass
(P4, 5,6,7)
Fourth check 0 1 1 1 Odd Fail
8
(P8, 9,10,11) 9

Thus, the 9th bit position is in error. Correct code word is 10110010011.
Convolutional Codes

Unlike block codes in which the check bits are computed for a block of data,
convolutional codes are generated over a “span” of data bits, e.g., a convolutional
code of constraint length 3 is generated bit by bit always using the “last 3 data bits”.
Figure 8 shows a simple convolutional encoder consisting of a shift register having
three stages and EXOR gates which generate two output bits for each input bit. It is
called a rate ½ convolutional encoder.

Fig. 8 Half-rate convolutional encoder.

State transition diagram of this encoder is shown in Fig. 9. Each circle in the diagram
represents a state of the encoder, which is the content of two leftmost stages of the
shift register. There are four possible states 00, 01, 10, 11. The arrows represent the
state transitions for the input bit which can be 0 or 1. The label on each arrow shows
the input data bit by which the transition is caused and the corresponding output bits.
As an example, suppose the initial state of the encoder is 00 and the input data
sequence is 1011. The corresponding output sequence of the encoder will then be
11010010.

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Trellis Diagram. An alternative way of representing the states is by using the trellis
diagram (Fig. 10). Here the four states 00, 01, 11, 10 are represented as four levels.
The arrows represent state transitions as in the state transition diagram. The labels on
the arrows indicate the output. By convention, a “0” input is always represented as an
upward transition and a “1” input as a downward transition. The trellis diagram can
be obtained from the state transition diagram.
EXAMPLE 11

Generate the convolutional code using the trellis diagram of Fig . 10 for the input bit
sequence 0101 assuming the encoder is in state A to start with.

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Solution
Starting from state A at top left corner in Fig . 10 and tracing the path through the
trellis for the input sequence 0101, we get

Present Input Next Output

sate bit state bits

A 0 A 00
A 1 C 11
C 0 B 01
B 1 C 00

Output bit sequence 0 0 1 1 0 1 0 0

Decoding Algorithm. Decoder for the convolutional code is based on the maximum
likelihood principle called the Viterbi algorithm. Knowing the encoder behavior and
the received sequence of bits, we can find the most likely transmitted sequence by
analyzing all the possible paths through the trellis. The path which results in the
output sequence which is nearest to the received sequence is chosen and the
corresponding input bits are the decoded data bits.
Let the data bit sequence be 1011 which is encoded as 11010010 using the
encoder shown in Fig. 8. The received sequence is 11110010 having an error in the
third bit position.
Now we need to analyze all possible paths through the trellis and select the path
which results in an output sequence nearest the received sequence. We will do it in
two steps. After the first step we will be in a position to exclude further analysis of
some of the paths.
Step 1: Let us first analyze the first three pairs of bits, that is, 111100. If we start
from state A and trace all possible paths through the trellis shown in Fig. 10, we get
the output bit sequences, and their distances from the received sequence 111100 as
given in Table 2.
Table 2 Alternative Paths through the Trellis

Step1 Step2
Data Path Output Distance Next Next Output Distance
Bits sequence from data state sequence from
111100 bit 11110010

000 AAAA 000000 4

100 ACBA 110111 3+ 0 A 11011100 4
1 C 11011111 3
110 ACDB 111010 2+ 0 A 11101011 3
1 C 11101000 3
010 AACB 001101 3
001 AAAC 000011 6
101 ACBC 110100 1+ 0 B 11010001 3
1 D 11010010 1+
111 ACDD 111001 2+ 0 B 11100110 2
1 D 11100101 4
011 AACD 001110 3
+ chosen paths having smaller distance.

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Note that a pair of paths terminate on each state, e.g., state A can be reached via
AAAA or ACBA. But path AAAA results in output sequence 000000 which is at a
distance of 4 from the first six bits of the received sequence. In the case of the other
path ACBA, this distance is only 3. Because we are looking for a sequence with the
smallest distance, we
need not consider the first path for further analysis. We can drop some more paths in
similar manner.

Step 2: Having considered the first three pairs of bits, let us move further. Transitions
from the last state arrived at in the first step, will result in two potential states
depending on the next input bit. Distances of the resulting bit sequences from the
received sequence are given in Table 2. Note that we have computed the distances for
only the selected paths of the first step. The minimum distance is for the path ACBCD
which corresponds to the correct data bit sequence 1011.

EXAMPLE 12

What is the message sequence if the received rate ½ encoded bit sequence is
00010100? Use the trellis diagram given in Fig. 10.
Solution

Step1 Step2
Data Path Output Distance Next Next Output
Distance
Bits sequence from data state sequence from
000101 bit
00010100
000 AAAA 000000 2 0 A 00000000
2
1 C 00000011
4
100 ACBA 110111 3
110 ACDB 111010 6
010 AACB 001101 1 0 A 00110111
3
1 C 00110100
1
001 AAAC 000011 2 0 B 00001101
3
1 D 00001110
2
101 ACBC 110100 3
111 ACDD 111001 4
011 AACD 001110 3 0 B 00111010
4
1 D 00111001
4
from the above table, it can be seen that minimum distance is for the path AACBC
which corresponds to the message bit sequence 0101.

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REVERSE ERROR CORRECTION

We have seen some of the methods of forward error correction but reverse error
correction is more economical than forward error correction in terms of the number of
check bits. Therefore, usually error detection methods are implemented with an error
correction mechanism which requires the receiver to request the sender for
retransmission of the code word received with errors. There are three basic
mechanisms of reverse error correction:
1. Stop and wait
2. Go-back-N
3. Selective retransmission
Stop and wait
In this scheme, the sending end transmits one block of data at a time and then waits
for acknowledgement from the receiver. If the receiver detects any error in the data
block, it sends a request for retransmission in the form of negative acknowledgement.
If there is no error, the receiver sends a positive acknowledgement in which case the
sending end transmits, the next block of data. Figure 11 illustrates the mechanism.
sender Receiver
No
Data Block Errors
with Check - --------------
bits
Positive
Acknowledgement
----------------
Errors
Next Data Detected
Block --------------
Negative
Acknowledgement
---------------

Retransmission
---------------
Fig . 11 Reverse error correction by stop-and-wait mechanism.
Go-Back-N
In this mechanism all the data blocks are numbered and the sending end keeps
transmitting the data blocks with check bits. Whenever the receiver detects error in a
block, it sends a retransmission request indicating the sequence number of the data
block received with errors. The sending end then starts retransmission of all the data
blocks from the requested data block onwards (Fig.12).
Selective Retransmission
If the receiver is equipped with the capability to resequence the data blocks, it
requests for selective retransmission of the data block containing errors. On receipt of
the request, the sending end retransmits the data block but skips the following data
blocks already transmitted and continues with the next data block (Fig. 13).In data
communications, we use reverse error correction using one of the mechanisms
described above.

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Sender Receiver
Data Block 1 1
With check
Bits
Errors
2
Detected

3 3

Request for
2 2 Retransmission
Of Data Block 2

2 2

3 3

Fig. 12 Reverse error correction by go-back-N Mechanism

Sender Receiver
Data Block 1 1 No
With Check -- Errors
Bits
Errors
2 Detected
--

3 3

Request for
2 2 Retransmission
Of Data Block 2

2 2

4 4

Fig. 13 Reverse error correction by selective retransmission mechanism.

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SUMMARY

Errors are introduced due to imperfections in the transmission media. For error
control, we need to detect the errors and then take corrective action. Parity bits,
checksum and cyclic redundancy check (CRC) are some of the error detection
methods. Out of the three, CRC is the most powerful and widely implemented.

Error correction methods include forward error correction or reverse error correction.
Forward error correction requires additional check bits which enable the receiver to
correct the errors as well. However, reverse errors correction mechanisms, namely,
stop and wait, go-back-N or selective retransmission are more common. In these
mechanisms the receiver requests for retransmission of the data blocks received with
errors.

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