SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121C DECEMBER 1982 REVISED DECEMBER 2002

D D D D D D D D D D

Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd = 13 ns 4-mA Output Drive at 5 V Low Input Current of 1 A Max Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control

SN54HC191 . . . J OR W PACKAGE SN74HC191 . . . D, N, OR NS PACKAGE (TOP VIEW)

B QB QA CTEN D/U QC QD GND

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VCC A CLK RCO MAX/MIN LOAD C D

SN54HC191 . . . FK PACKAGE (TOP VIEW)

The outputs of the four flip-flops are triggered on a low- to high-level transition of the clock (CLK) input if the count-enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, it counts down.

NC No internal connection

ORDERING INFORMATION
TA PDIP N 40C to 85C 40 SOIC D SOP NS CDIP J 55C to 125C CFP W LCCC FK PACKAGE Tube Tube Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74HC191N SN74HC191D SN74HC191DR SN74HC191NSR SNJ54HC191J SNJ54HC191W SNJ54HC191FK TOP-SIDE MARKING SN74HC191N HC191 HC191 SNJ54HC191J SNJ54HC191W

SNJ54HC191FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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QD GND NC D C

The HC191 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.

QB B NC VCC A QA CTEN NC D/U QC

4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

description/ordering information

CLK RCO NC MAX/MIN LOAD

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121C DECEMBER 1982 REVISED DECEMBER 2002

description/ordering information (continued)

These counters feature a fully independent clock circuit. Change at the control (CTEN and D/U) inputs that modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the condition meeting the stable setup and hold times. These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs. Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum (MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15) counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low. The counters can be cascaded easily by feeding RCO to CTEN of the succeeding counter if parallel clocking is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed operation.

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121C DECEMBER 1982 REVISED DECEMBER 2002

logic diagram (positive logic)

12 4 13 D/U CLK LOAD A 5 14 11 15 S C1 1D R 1 2 3 RCO

MAX/MIN

CTEN

QA

S C1 1D R

QB

10 6

S C1 1D R

QC

9 7

S C1 1D R

QD

Pin numbers shown are for the D, J, N, NS, and W packages.

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121C DECEMBER 1982 REVISED DECEMBER 2002

typical load, count, and inhibit sequence

The following sequence is illustrated below: 1. Load (preset) to binary 13 2. Count up to 14, 15 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 15, 14, and 13
LOAD A B C D

Data Inputs

CLK D/U CTEN QA QB QC QD MAX/MIN RCO 13 14 15 0 1 2 2 2 1 0 15 14 13

Data Outputs

Count Up Inhibit Load

Count Down

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121C DECEMBER 1982 REVISED DECEMBER 2002

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54HC191 MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 0 0 NOM 5 MAX 6 SN74HC191 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V

TA Operating free-air temperature 55 125 40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121C DECEMBER 1982 REVISED DECEMBER 2002

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = 20 A VOH VI = VIH or VIL IOH = 4 mA IOH = 5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 0.1 0.1 0.1 0.1 0.26 0.26 100 8 10 SN54HC191 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1000 160 10 MAX SN74HC191 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1000 80 10 nA A pF V V MAX UNIT

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121C DECEMBER 1982 REVISED DECEMBER 2002

timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock frequency 4.5 V 6V 2V LOAD low tw Pulse duration CLK high or low 4.5 V 6V 2V 4.5 V 6V 2V Data before LOAD 4.5 V 6V 2V CTEN before CLK tsu Setup time D/U before CLK 4.5 V 6V 2V 4.5 V 6V 2V LOAD inactive before CLK 4.5 V 6V 2V Data after LOAD 4.5 V 6V 2V th Hold time CTEN after CLK 4.5 V 6V 2V D/U after CLK 4.5 V 6V 120 24 21 120 24 21 150 30 25 205 41 35 205 41 35 150 30 25 5 5 5 5 5 5 5 5 5 TA = 25C MIN MAX 4.2 21 24 180 36 31 180 36 31 230 46 38 306 61 53 306 61 53 225 45 38 5 5 5 5 5 5 5 5 5 SN54HC191 MIN MAX 2.8 14 16 150 30 26 150 30 26 188 38 32 255 51 44 255 51 44 190 38 32 5 5 5 5 5 5 5 5 5 ns ns ns SN74HC191 MIN MAX 3.3 17 19 MHz UNIT

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121C DECEMBER 1982 REVISED DECEMBER 2002

switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V LOAD Any Q 4.5 V 6V 2V A, B, C, or D QA, QB, QC, or QD 4.5 V 6V 2V RCO 4.5 V 6V 2V CLK tpd d MAX/MIN Any Q 4.5 V 6V 2V 4.5 V 6V 2V RCO D/U MAX/MIN 4.5 V 6V 2V 4.5 V 6V 2V CTEN RCO 4.5 V 6V 2V tt Any 4.5 V 6V MIN 4.2 21 24 TA = 25C TYP MAX 8 42 48 130 40 33 135 36 30 58 17 14 107 31 26 123 39 32 102 29 24 86 24 20 50 15 13 38 8 6 264 53 45 240 48 41 120 24 21 192 38 32 252 50 43 228 46 38 192 38 32 132 26 23 75 15 13 SN54HC191 MIN 2.8 14 16 396 79 67 360 72 61 180 36 31 288 58 49 378 76 65 342 68 59 288 58 49 198 40 34 110 22 19 MAX SN74HC191 MIN 3.3 17 19 330 66 56 300 60 51 150 30 26 240 48 41 315 63 54 285 57 49 240 48 41 165 33 28 95 19 16 ns ns MHz MAX UNIT

operating characteristics, TA = 25C

PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 50 UNIT pF

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121C DECEMBER 1982 REVISED DECEMBER 2002

PARAMETER MEASUREMENT INFORMATION

High-Level Pulse VCC 50% tw Low-Level Pulse VCC 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC 50% tPLH Reference Input tsu Data Input 50% 10% 90% 50% th 90% VCC 50% 10% 0 V tf Out-of-Phase Output VCC 0V In-Phase Output 50% 10% tPHL 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL 50% 0V

From Output Under Test

Test Point CL = 50 pF (see Note A)

Input

tr

VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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MECHANICAL DATA
MCER002C JANUARY 1995 REVISED JUNE 1999

J (R-GDIP-T**)
14 LEADS SHOWN

CERAMIC DUAL-IN-LINE

PINS ** DIM A MAX B 14 8 A MIN

14 0.310 (7,87) 0.290 (7,37) 0.785 (19,94) 0.755 (19,18) 0.300 (7,62) 0.245 (6,22)

16 0.310 (7,87) 0.290 (7,37) 0.785 (19,94) 0.755 (19,18) 0.300 (7,62) 0.245 (6,22)

20 0.310 (7,87) 0.290 (7,37) 0.975 (24,77) 0.930 (23,62) 0.300 (7,62) 0.245 (6,22)

B MAX C B MIN

1 0.065 (1,65) 0.045 (1,14)

C MAX

C MIN

0.100 (2,54) 0.070 (1,78)

0.020 (0,51) MIN

0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20)

015

4040083/E 03/99 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package is hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, and GDIP1-T20

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MECHANICAL DATA
MLCC006B OCTOBER 1996

FK (S-CQCC-N**)
28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

18

17

16

15

14

13

12

NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20

A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)

B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)

19 20 21 B SQ 22 A SQ 23 24 25

26

27

28

4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)

0.020 (0,51) 0.010 (0,25)

0.055 (1,40) 0.045 (1,14)

0.045 (1,14) 0.035 (0,89)

0.028 (0,71) 0.022 (0,54) 0.050 (1,27)

0.045 (1,14) 0.035 (0,89)

4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004

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MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002

N (R-PDIP-T**)
16 PINS SHOWN

PLASTIC DUAL-IN-LINE PACKAGE

PINS ** DIM A 16 9 A MAX

14 0.775 (19,69) 0.745 (18,92)

16 0.775 (19,69) 0.745 (18,92)

18 0.920 (23,37) 0.850 (21,59)

20 1.060 (26,92) 0.940 (23,88)

A MIN

0.260 (6,60) 0.240 (6,10)

MS-100 VARIATION

AA

BB

AC

AD

1 0.070 (1,78) MAX

0.035 (0,89) MAX

0.020 (0,51) MIN

0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gauge Plane

0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M

0.430 (10,92) MAX

14/18 PIN ONLY 20 pin vendor option

D 4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

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MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001

D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)

PLASTIC SMALL-OUTLINE PACKAGE

0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)

0.008 (0,20) NOM

Gage Plane 1 A 4 0 8 0.044 (1,12) 0.016 (0,40)

0.010 (0,25)

Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)

PINS ** DIM A MAX A MIN

8 0.197 (5,00) 0.189 (4,80)

14 0.344 (8,75) 0.337 (8,55)

16 0.394 (10,00) 0.386 (9,80)

4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012

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MECHANICAL DATA
MSOP002 OCTOBER 1994

NS (R-PDSO-G**)
14 PINS SHOWN 1,27 14 8 0,51 0,35 0,25 M

PLASTIC SMALL-OUTLINE PACKAGE

0,15 NOM 5,60 5,00 8,20 7,40

Gage Plane 1 A 7 0 10 0,25 1,05 0,55

Seating Plane 2,00 MAX 0,05 MIN PINS ** DIM A MAX 14 16 20 24 0,10

10,50

10,50

12,90

15,30

A MIN

9,90

9,90

12,30

14,70

4040062 / B 02/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

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