SN54/74LS196

4-STAGE PRESETTABLE SN54/74LS197

RIPPLE COUNTERS
The SN54/74LS196 decade counter is partitioned into divide-by-two and di-
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)
sequence or in a bi-quinary mode producing a 50% duty cycle output. The 4-STAGE PRESETTABLE
SN54/74LS197 contains divide-by-two and divide-by-eight sections which RIPPLE COUNTERS
can be combined to form a modulo-16 binary counter. Low Power Schottky
LOW POWER SCHOTTKY
technology is used to achieve typical count rates of 70 MHz and power dis-
sipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)
overrides clocked operations and asynchronously loads the data on the Par-
allel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits
J SUFFIX
usable as programmable counters. The circuits can also be used as 4-bit CERAMIC
latches, loading data from the Parallel Data inputs when PL is LOW and stor- CASE 632-08
ing the data when PL is HIGH. 14
1
• Low Power Consumption — Typically 80 mW
• High Counting Rates — Typically 70 MHz
• Choice of Counting Modes — BCD, Bi-Quinary, Binary
• Asynchronous Presettable N SUFFIX
• Asynchronous Master Reset PLASTIC
• Easy Multistage Cascading 14 CASE 646-06
• Input Clamp Diodes Limit High Speed Termination Effects 1

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC MR Q3 P3 P1 Q1 CP0 D SUFFIX
14 13 12 11 10 9 8 SOIC
14
1 CASE 751A-02

NOTE:
The Flatpak version
has the same pinouts ORDERING INFORMATION
(Connection Diagram) as
the Dual In-Line Package. SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
1 2 3 4 5 6 7 SN74LSXXXD SOIC
PL Q2 P2 P0 Q0 CP1 GND

PIN NAMES LOADING (Note a) LOGIC SYMBOL

HIGH LOW
1 4 10 3 11
CP0 Clock (Active LOW Going Edge) 1.0 U.L. 1.5 U.L.
Input to Divide-by-Two Section
PL P0 P1 P2 P3
CP1 (LS196) Clock (Active LOW Going Edge) 2.0 U.L. 1.75 U.L. 8 CP0
Input to Divide-by-Five Section
6 CP1 MR Q0 Q1 Q2 Q3
CP1 (LS197) Clock (Active LOW Going Edge) 1.0 U.L. 0.8 U.L.
Input to Divide-by-Eight Section
MR Master Reset (Active LOW) Input 1.0 U.L. 0.5 U.L. 13 5 9 2 12
PL Parallel Load (Active LOW) Input 0.5 U.L. 0.25 U.L.
VCC = PIN 14
P0–P3 Data Inputs 0.5 U.L. 0.25 U.L.
GND = PIN 7
Q0–Q3 Outputs (Notes b, c) 10 U.L. 5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
c. In addition to loading shown, Q0 can also drive CP1.

FAST AND LS TTL DATA

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 SN54/74LS196 • SN54/74LS197

LOGIC DIAGRAM

P0 P1 P2 P3
13 4 10 3 11
MR
PL
1

J SD Q J SD Q J SD Q J SD Q
8
CP0
K CD Q K CD Q K CD Q K CD Q

6
CP1
5 9 2 12
Q0 Q1 Q2 Q3

LS196

P0 P1 P2 P3
13 4 10 3 11
MR
PL
1

J SD Q J SD Q J SD Q J SD Q
8
CP0
K CD Q K CD Q K CD Q K CD Q

6
CP1
5 9 2 12
Q0 Q1 Q2 Q3

LS197

VCC = PIN 14
GND = PIN 7
= PIN NUMBERS

FAST AND LS TTL DATA

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 SN54/74LS196 • SN54/74LS197

FUNCTIONAL DESCRIPTION
The LS196 and LS197 are asynchronously presettable de- significant output.
cade and binary ripple counters. The LS196 Decade Counter The LS196 Decade Counter can be connected up to oper-
is partitioned into divide-by-two and divide-by-five sections ate in two different count sequences, as indicated in the tables
while the LS197 is partitioned into divide-by-two and divide- of Figure 2. With the input frequency connected to CP0 and
by-eight sections, with all sections having a separate Clock in- with Q0 driving CP1, the circuit counts in the BCD (8, 4, 2, 1)
put. In the counting modes, state changes are initiated by the sequence. With the input frequency connected to CP1 and Q3
HIGH to LOW transition of the clock signals. State changes of driving CP0, Q0 becomes the low frequency output and has a
the Q outputs, however, do not occur simultaneously because 50% duty cycle waveform. Note that the maximum counting
of the internal ripple delays. When using external logic to de- rate is reduced in the latter (bi-quinary) configuration because
code the Q outputs, designers should bear in mind that the un- of the interstage gating delay within the divide-by-five section.
equal delays can lead to decoding spikes and thus a decoded The LS196 and LS197 have an asynchronous active LOW
signal should not be used as a clock or strobe. The CP0 input Master Reset input (MR) which overrides all other inputs and
serves the Q0 flip-flop in both circuit types while the CP1 input forces all outputs LOW. The counters are also asynchronously
serves the divide-by-five or divide-by-eight section. The Q0 presettable. A LOW on the Parallel Load input (PL) overrides
output is designed and specified to drive the rated fan-out plus the clock inputs and loads the data from Parallel Data (P0 – P3)
the CP1 input. With the input frequency connected to CP0 and inputs into the flip-flops. While PL is LOW, the counters act as
Q0 driving CP1, the LS197 forms a straightforward module-16 transparent latches and any change in the Pn inputs will be re-
counter, with Q0 the least significant output and Q3 the most flected in the outputs.

Figure 2. LS196 COUNT SEQUENCES

DECADE (NOTE 1) BI-QUINARY (NOTE 2)
COUNT Q3 Q2 Q1 Q0 COUNT Q0 Q3 Q2 Q1
0 L L L L 0 L L L L
1 L L L H 1 L L L H
2 L L H L 2 L L H L
3 L L H H 3 L L H H
4 L H L L 4 L H L L
5 L H L H 5 H L L L
6 L H H L 6 H L L H
7 L H H H 7 H L H L
8 H L L L 8 H L H H
9 H L L H 9 H H L L
NOTES:
1. Signal applied to CP0, Q0 connected to CP1.
2. Signal applied to CP1, Q3 connected to CP0.

MODE SELECT TABLE

INPUTS
RESPONSE
MR PL CP
L X X Reset (Clear)
H L X Parallel Load
H H Count
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
= HIGH to Low Clock Transition

FAST AND LS TTL DATA

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 SN54/74LS196 • SN54/74LS197

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

Input HIGH Current

Data, PL 20
MR, CP0 (LS196) 40 µA VCC = MAX, VIN = 2.7 V
MR, CP0, CP1 (LS197) 40
IIH CP1 (LS196) 80
Data, PL 0.1
MR, CP0 (LS196) 0.2
mA VCC = MAX, VIN = 7.0 V
MR, CP0, CP1 (LS197) 0.2
CP1 (LS196) 0.4
Input LOW Current
Data, PL – 0.4
MR – 0.8
IIL mA VCC = MAX, VIN = 0.4 V
CP0 – 2.4
CP1 (LS196) – 2.8
CP1 (LS197) – 1.3
IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX
ICC Power Supply Current 27 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

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 SN54/74LS196 • SN54/74LS197

AC CHARACTERISTICS (TA = 25°C)

Limits
LS196 LS197
Symbol
S b l Parameter
P Min Typ Max Min Typ Max Unit
U i Test
T C
Conditions
di i
fMAX Maximum Clock Frequency 30 40 30 40 MHz
tPLH CP0 Input to 8.0 15 8.0 15
ns
tPHL Q0 Output 13 20 14 21

tPLH CP1 Input to 16 24 12 19

ns
tPHL Q1 Output 22 33 23 35

tPLH CP1 Input to 38 57 34 51

ns
tPHL Q2 Output 41 62 42 63 VCC = 5.0
50V
tPLH CP1 Input to 12 18 55 78 CL = 15 pF
ns
tPHL Q3 Output 30 45 63 95

tPLH 20 30 18 27
Data to Output ns
tPHL 29 44 29 44

tPLH PL Input to 27 41 26 39
ns
tPHL Any Output 30 45 30 45

tPHL MR Input to Any Output 34 51 34 51 ns

AC SETUP REQUIREMENTS (TA = 25°C)

Limits
LS196 LS197
S b l
Symbol P
Parameter Min Typ Max Min Typ Max U i
Unit T
Test C
Conditions
di i
tW CP0 Pulse Width 20 20 ns
tW CP1 Pulse Width 30 30 ns
tW PL Pulse Width 20 20 ns
tW MR Pulse Width 15 15 ns
ts Data Input Setup Time — HIGH 10 10 ns VCC = 5.0
50V
ts Data Input Setup Time — LOW 15 15 ns
th Data Hold Time — HIGH 10 10 ns
th Data Hold Time — LOW 10 10 ns
trec Recovery Time 30 30 ns

DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required nition. A negative HOLD TIME indicates that the correct logic
for the correct logic level to be present at the logic input prior to level may be released prior to the clock transition from HIGH to
the clock transition from HIGH to LOW in order to be recog- LOW and still be recognized.
nized and transferred to the outputs.
RECOVERY TIME (trec) — is defined as the minimum time
HOLD TIME (th) — is defined as the minimum time following required between the end of the reset pulse and the clock
the clock transition from HIGH to LOW that the logic level must transition from HIGH to LOW in order to recognize and transfer
be maintained at the input in order to ensure continued recog- LOW Data to the Q outputs.

FAST AND LS TTL DATA

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 SN54/74LS196 • SN54/74LS197

AC WAVEFORMS

CP 1.3 V 1.3 V
tW(H)
tPLH
tPHL
Q 1.3 V 1.3 V

Figure 1

Pn 1.3 V 1.3 V Pn
tPHL tPLH tW

1.3 V PL 1.3 V
Qn
tPLH tPHL

Qn 1.3 V
NOTE: PL = LOW

Figure 2 Figure 3

Pn* 1.3 V 1.3 V

th(H) th(L)
PL OR MR 1.3 V ts(H) ts(L)
tW trec PL 1.3 V 1.3 V

CP 1.3 V
tPHL Qn* Q=P Q=P

Q 1.3 V
* The shaded areas indicate when the input is permitted
* to change for predictable output performance

Figure 4 Figure 5

FAST AND LS TTL DATA

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