EE 552 (Logic Design and Switching Theory) Project: Quantitative Measurement of The Benefits of Reduction Techniques For Asynchronous Finite State Machines

EE 552 (Logic design and switching theory) Project: Quantitative measurement of the benefits of reduction techniques for asynchronous
finite state machines.
Purushotham Kamath pkamath@usc.edu
I alone prepared and wrote this project. I received no help from anyone one else. This material is not copied or paraphrased from any other source except where specifically indicated. I grant my permission for this project to be placed on the course homepage during future semesters. I understand that I could receive an F for the course retroactively, even after graduation, if this work is later found to be plagiarized.
Contents 1. 0 Introduction.................................................................................... 4 2.0 The finite state machine ................................................................... 5 3.0 Circuit design of the finite state machine........................................... 6 4.0 Component design .......................................................................... 7 5.0 Verilog behavioral modeling............................................................. 8 6.0 Simulation results and conclusions ................................................... 8 7.0 References...................................................................................... 9
1. 0 Introduction
Logic design and switching theory deals with techniques to reduce the amount of logic (both combinational and sequential) required to build a finite state machine [Ell] [Fried]. Some of the techniques involved in the reduction of asynchronous finite state machines include Algorithms to transform and simplify Huffman machines. Row reduction of completely and incompletely specified state machines. Asynchronous machine state assignment.
Using these algorithms finite state machines are reduced to simpler forms, resulting in gains in the speed of the circuit and a reduction in the number of combinational and sequential components used. This project attempts to quantitatively measure the improvements that may be obtained from an application of these techniques to a simple asynchronous finite state machine. The following methodology was used to evaluate the A simple finite state machine was designed. The finite machine was chosen so that it was easy to quantitatively determine the performance improvements obtained from the application of two techniques: Normalization and Row Reduction. Circuits were designed to implement the finite state machines in various states of row reduction i.e. with different numbers of state. The components required to model the circuit were designed using static CMOS logic. The component parameters were determined using analytical techniques. The circuits were modeled using Verilog hardware description language. Verilog behavioral models were implemented for the components and the circuits. The asynchronous finite state machines were simulated. The following measurements were obtained:
The delay in state change (time taken from the input change to machine settling in its final state). The delay in output change (0 to 1) (time taken for the machine output to change from 0 to 1, when a state change results in such a change). The delay in output change (1 to 0) (time taken for the machine output to change from 0 to 1, when a state change results in such a change). The number of sequential components required. The number of combinational components required.
2.0 The finite state machine

In order to measure the required parameters we use a state machine that can be progressively reduced to a simpler machine by means of Normalization and Row Reduction techniques. The state machine is intentionally chosen to be a very simple state machine, so that the techniques of normalization and row reduction can be applied repeatedly to reduce the number of states in the machine. At each stage of reduction the required measurements were taken. The state machine below was chosen: Input 0 1,0 2,0 3,0 4,0 5,0 6,0 7,0 7,0 Input 1 0,1 0,0 1,0 2,0 3,0 4,0 5,0 6,0
State 0 1 2 3 4 5 6 7
The above machine can be reduced to the simple machine Input 0 1,0 1,0 Input 1 0,1 0,0
State 0 1
However to evaluate the improvement in speed that we obtain, we reduce the number of states in steps of 1. Note that in reality most machines will not be able to be reduced to such a simple form. However the measurements do give an idea of the improvements that are likely if a machine is reduced to a simpler form.
3.0 Circuit design of the finite state machine
Combinational Logic
State Memory
The circuit is designed using combination and sequential logic. While designing the combinational circuits there are two issues to be noted: The delay elements are modeled as D flip flops that latch the input when it changes. The combinational logic elements are built in the form of sum of product forms and are implemented using AND-OR logic gate.
4.0 Component design

An implementation of the state diagram when reduced to 8,7,6,5,4,3 and 2 states indicates that the gates required are 1. AND gates: 2 input, 3 input, 4 input 2. OR gates: 2 input, 4 inputs, 6 inputs, 8 inputs. The gates have been designed using static CMOS logic with the following restrictions: All components have been designed for minimum size. The delay of each component is modeled by assuming that the delay is proportional to the resistance of the charging/discharging path of that component. The charging/discharging resistance of a component is the sum of the resistances of the transistors in its charging discharging path. The resistance of a transistor is inversely proportional to the W/L ratio (Width to Length ratio) of the transistor used. Since we are designing for minimum size, we assume all transistors are designed using the minimum possible W/L. The delay of a standard static CMOS inverter is assumed to be the unit delay. The longer of the charging or discharging delay used as the delay for the component (Discharging takes longer for AND gates, charging takes longer for the OR gates).
The design of the static inverter, 2 input AND gate and 2 input OR gate are shown on the following page We assume the delay of a standard static CMOS inverter is 207.1 ps (0.2071ns) [Rab] Delay of the 2 input AND gate = 2 * Delay of the inverter = 414 ps (Discharging delay) Delay of the 2 input OR gate = 2 * Delay of the inverter=414 ps (Charging delay) Similarly, delay of the 3 input AND gate = 3 * Delay of the inverter= 621 ps
The values of the delays for other gates are below: Gate AND AND AND OR OR OR OR Number of inputs 2 3 4 2 4 6 8 Delay (ps) 414 621 828 414 828 1242 1656
5.0 Verilog behavioral modeling

Verilog is a hardware description language used for behavioral modeling [Tzart]. The language may be used to model components and circuits at varying degrees of complexity. The circuits can be simulated with different component parameters, different inputs and Each component was modeled and the finite state machines were modeled by building them from the components. The following Verilog behavioral model files are appended (These are some of the components/circuits used in the simulation). 1. 2 input AND gates 2. 2 input OR gates 3. Finite state machine for an 8state machine.
6.0 Simulation results and conclusions

The following results were obtained:
Number of states
State change delay (ps)
8 7 6 5 4 3 2
38318 30360 25300 18584 13347 8070 3828
Output change delay (1->0) (ps) 818 818 818 818 621 621 414
Output change delay (0->1) (ps) 39136 31178 26118 19402 13968 8691 4242
Average output change delay (ps) 19977 15998 13468 10110 7294 4656 2431
Number of sequential components 3 3 3 3 2 2 1
Number of combinational components 32 26 22 18 14 10 6
Observations from the results indicate that normalization reduces the delay by reducing the number of cycles through the delay elements while row reduction reduces the number of components (combinational and sequential) by reducing the number of bits required for storing the state. A reduction in the number of states results in an improvement in the speed of the circuit. The results are plotted in the following graphs.
7.0 References
[Ell] Techniques in advanced switching theory - James Ellison [Fried] Theory and design of switching circuits - Friedman and Menon (Computer Press Inc.) [Rab] Digital Integrated Circuits- A design perspective - Jan Rabaey (Prentice Hall, 1996) [Tzar] Verilog Behavioral Modeling - Lecture notes by Nestor Tzartzanis available at http://www-scf.usc.edu/~ee577/cad_frame.html

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EE 552 (Logic design and switching theory) Project: Quantitative measurement of the benefits of reduction techniques for asynchronous

finite state machines.

Purushotham Kamath pkamath@usc.edu

2.0 The finite state machine

3.0 Circuit design of the finite state machine

4.0 Component design

5.0 Verilog behavioral modeling

6.0 Simulation results and conclusions

State change delay (ps)

38318 30360 25300 18584 13347 8070 3828

Number of sequential components 3 3 3 3 2 2 1

Number of combinational components 32 26 22 18 14 10 6

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