IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO.

2, FEBRUARY 1998

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Current-Mode Versus Voltage-Mode Biquad Filters: What the Theory Says

Jirayuth Mahattanakul and Chris Toumazou, Member, IEEE
Abstract As there is a growing interest in the design of so called current-mode lters, this paper is concerned with an investigation into the general performance criteria and the speed/dynamic range limits of current-mode Gm -C based lters, compared to conventional voltage-mode Gm -C lters. It is shown here that, as far as speed, dynamic range, and power consumption are concerned and provided that both kinds of lter topology employ the same type of transconductors and capacitors, the result comes out in the favor of the use of the voltage-mode lter processing as a solution for realizing high performance Gm -C lters. Index Terms Analog design, current-mode circuits, lters.

Fig. 1. A second-order lter topology.

II. A REVIEW

OF

FILTERS

I. INTRODUCTION ECENTLY, there have been attempts at applying currentmode techniques to various kinds of electronic circuit design. Rather than representing the processing signal by voltage quantities, the current-mode technique involves using current signals. Current-mode signal processing may be dened as the processing of current signals in an environment where voltage signals are irrelevant in determining circuit performance [1]. This may be the case for circuits that are specically designed to operate with low impedance nodes such that voltage swings are small and time constants are short. However, the term current-mode has also be used to describe a system which has a current transfer function [2][11]. This is particularly true of the current-mode integrator and lter based - realizations. In these current-mode lters upon classical the active element used in the circuit is the transconductor. However, to convert from a voltage-mode transfer function to a current-mode transfer function the transconductors are simply repositioned in the lters. In this paper, we investigate and comprehensively compare the general performance criteria and inherent fundamental limits of the conventional voltage-mode - lter with recent so-called current-mode lter approaches. We will present a detailed theoretical analysis of both types and discuss advantages and disadvantages.

Manuscript received December 18, 1995; revised July 23, 1996. This paper was recommended by Editor J. Choma, Jr. J. Mahattanakul is with the Mahanakorn University of Technology, Bangkok 10530, Thailand. C. Toumazou is with the Department of Electrical and Electronic Engineering, Imperial College of Science, Technology, and Medicine, University of London, London SW7 2BT, U.K. Publisher Item Identier S 1057-7130(98)01640-1.

Excluding direct realization, there are generally three methods for realizing low-sensitivity designs of high-order lters, namely, the cascade approach, the multiple-loop feedback or coupled-biquad approach, and the ladder simulation approach [12]. In the rst two methods, the high-order function is factorized into subnetworks of second-order sections. The resulting second-order biquad network can be considered as an intermediate building block for high-order lters. As shown in the block diagram of Fig. 1, the second-order lter itself is, in turn, composed of two integrators embedded in negative feedback loops. As a result, most CT lters contain integrators as basic building blocks. Generally, four types of operational amplier, namely voltage-controlled voltage source (voltage amplier), voltagecontrolled current source (transconductance amplier), current-controlled current source (current amplier), and current-controlled voltage source (transresistance amplier) exist. However, most work on high-frequency lters concentrate upon the transconductance amplier. To - lters are the most popular technique used in date, implementing integrated high frequency continuous-time lters [13]. Their popularity stems from the fact that the transconductors are very easy to implement in monolithic form, transconductors generally have higher bandwidth than operational ampliers, can be tuned electronically, and can lead to simple circuitry [14]. - integrator which Fig. 2(a) shows a conventional comprises a transconductor, used for converting an input voltage to a proportional amount of current, and an integrating capacitor, used for integrating and converting the current back to voltage form. - second-order lter can be obtained by connecting A integrators of Fig. 2(a) in feedback as shown in Fig. 1. A typical example is shown in the circuit of Fig. 2(b) which simultaneously provides both low-pass and bandpass output

10577130/98$10.00 1998 IEEE

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(a)

(a)

(b) (b) Fig. 2. (a) A voltage-mode biquad lter.

Gm -C

integrator. (b) A voltage-mode

Gm -C

Fig. 3. (a) A current-mode biquad lter.

Gm -C

integrator. (b) A current-mode

Gm -C

voltage. The integrator and the lter circuit shown in Fig. 2 are - integrator and a voltage-mode a voltage-mode biquad lter, respectively, for the reason that both of their input and output signals are represented by voltage quantities. - current-mode integrator and Alternatively, a typical biquad lter are shown in Fig. 3(a) and (b), respectively, in which now the input and output signals are currents. It can be seen that the circuit components of both the voltageand current-mode circuits are essentially the same; the only difference being their ordering arrangement. As such, the current-mode circuits of Fig. 3 could be classied as integrators/lters as opposed to the - integrators/lters of Fig. 2. Note that if transconductor and are excluded from the lters of Fig. 2(b) and (c), the resulting circuits are identical, i.e., they become the core positive-feedback loop of the - oscillators which can provide either oscillating voltage (by tapping the voltage across or ) or oscillating current (by copying output current of transconductor or ). The voltage transfer function of the circuit of Fig. 2(b) and the current transfer function of the circuit of Fig. 3(b) are the same and given by

the small signal operation at every frequency of both circuits is the same. The identical transfer functions also implies that the nonlinearity of both circuits caused by the nonlinear characteristic of the transconductors and the capacitors should be the same. Therefore, we can expect that both circuits possess the same degree of linearity. Although both small and large signal operation of both lter types may be the same, some of the other important features such as power supply voltage and current, power consumption, dynamic range, etc., will differ and it is these performance differences which are the subject of this paper.

A. Transconductor Considerations - integrator/lter relies heavily The performance of a upon the various characteristics of the transconductor employed. The main focus in this section is on linearity and noise of the transconductor since both of them have a major inuence on a dynamic range which is a very important performance criterior for the integrator/lter particularly for radio frequency (RF) applications. The literature available on high frequency transconductor design is exhaustive. We describe simple generic examples here purely for comparative purposes and not to present state of the art design. The circuits of Fig. 4(a) and (b) are transconductors which exploit the characteristic of the bipolar transistor operating in forward active region and MOSFET operating in saturation region, respectively. The transconductance of these circuits is the transconductance of the driver transistors and can be varied by changing bias currents. The differential form of the transconductor of Fig. 4(a) and (b) are shown in Fig. 4(c) and (d), respectively. The advantage of using a differential structure is that the linearity of the output signal is improved by the absence of even-order distortion.

(1) and

(2) is the transconductance function of the transconwhere , respectively. ductor Since the voltage-mode and the current-mode biquad lters are essential the adjoint [7] of each other, the sensitivity and

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(a)

(b)

(c) Fig. 4. Simple transconductor: (a), (b) single-ended circuit and (c), (d) differential circuit.

(d)

(a)

(b) Fig. 5. (a) Transconductor design of [2] and (b) transconductor design of [3].

Various attempts can be made to increase the linearity of the transconductors of Fig. 4. However, since tradeoff between linearity and speed/noise is common in transconductor design,

the more linear transconductor is more likely to be a low speed and noisy one. For example, the linearity of the transconductor of Fig. 4 can be improved by emitter/source degeneration but

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distortion and an amplitude-dependent transconductance [13]. Thus to avoid these problems, the level of the input voltage must be kept small enough so that the transconductor exhibits linear conversion. For example, when the transconductor of Fig. 4(d) is driven by a pair of balanced signals, its transconductance gain can be found to be (3) is the amplitude of the input voltage and , the where . small-signal transconductance gain, equals It can be seen from (3) that only when is much smaller than , the transconductance gain of the . Under such conditions, circuit is largely independent of the dominant harmonic distortion of , HD3, can be found to be HD3 (4)

(a)

(b) Fig. 6. CCII-based transconductor.

at the expense of lower transconductance gain, lower speed, and higher noise. - lters that Because of the simple structures, the employ the transconductors of Fig. 4 can operate at very high frequency but obviously the distortion of their output signal will be considerably high as well. This is the case for the highfrequency current-mode lter designs of [2] and [3] where the current-mode integrator design of [2] and [3] are shown in Fig. 5(a) and (b), respectively. It can be clearly seen that the transconductor part of the circuit of Fig. 5(a) is similar to the transconductor of Fig. 4(b), i.e., it consists of the metaloxidesemiconductor (MOS) transistor(s) acting as a nonlinear converters connected to the current source(s). are assumed to be In the circuit of Fig. 5(b), if ideal and almost perfectly matched (since there is a positive feedback loop in the circuit and so if they are ideal and perfectly matched, the circuit will be dc unstable), it can be shown that the current owing into the grounded capacitor is and the actual circuit can be reduced to an equivalent transconductor shown on the right of Fig. 5(b). Therefore the similarity of the transconductor part of the circuit of Fig. 5(b) and the transconductor of Fig. 4(a) can now be seen. The design of current-conveyor (CCII)-based lters have been proposed in many research publications. Some of them - lters in disguise. [5], however, are nothing more than terminal is a Essentially a CCII with a resistor on its transconductor. Fig. 6(a) and (b) shows two ways of connecting a resistor with a CCII to form transconductance blocks. The basic schematic of the CCII itself is shown in Fig. 7. 1) Transconductor Linearity: Theoretically, the transconductance gain of the transconductor should remain constant regardless of the level of the input voltage. However, in practice this is only the case for a certain level of input voltage. Beyond that level the transconductance gain tends to deviate, i.e., the output current is not linearly dependent on the input voltage anymore. This will result both in an output signal

where where is the amplitude of the output current. Similarly when the transconductor of Fig. 4(c) is driven by a sinusoidal input voltages which is small enough to make the transconductance gain, , the dominant harmonic distortion of the output current can be expressed as HD3 (5)

Also when the CCII of Fig. 7(b) is directly used as a transconand ) and is ductance amplier ( sinusoidal and restricted to a small value so that , the dominant harmonic distortion of its output current is HD3 (6)

The implication of (4)(6) is that the ratio between the peak amplitude of the output current and the bias current, plays an important role in dictating the level of distortion of the output current. However, apart from the limited bias current, the level of power supply voltage also has an impact on the linearity of the circuit. This usually occurs when the voltage headroom of any circuit node approaches zero and the signal becomes - integrator clipped and distorted, e.g., in the case of the of Fig. 2(a) when it is driven by a low-frequency voltage. However in the circuits of interest, i.e., the biquad lters of Figs. 2(b) and 3(b), when single-stage transconductors are employed the ratio of the output current to bias current is the main factor of distortion. In these circuits the level of power supply voltage plays much less of a role in dictating the linearity of the circuit since the signals will be highly distorted by the limited bias current long before the voltage at any node reaches the level of supply voltage. The above discussion can be conrmed by rstly considering the graphs of Fig. 8 which are the plots of HD3 versus derived from (4) to (6). Since every nodes in the biquad lters of Figs. 2(b) and 3(b) are also the input terminal of the transconductor elements, it can

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(a)

(b)

(c) Fig. 7. (a) Basic schematic of CCII, (b) using single transistor, and (c) using mixed translinear loop (class AB complementary).

Fig. 8. Plot of jVin j versus HD3 of the transconductors of Fig. 4(d) [using (4) with IBIAS [using (5)] and Fig. 7(b) [using (6)].

100 A, k 0 = 100 A/V2 , and W = L], Fig. 4(c)

be seen from Fig. 8 that the voltage level of these nodes have to be restricted to a relatively much smaller value, compared to the usual supply voltage level, to keep the level of distortion of signal in a reasonable range. The conclusion is therefore that the level of supply voltage is not a main limited factor of the linearity of these circuits since the output current of the transconductor usually drives the device out of the linear region well before voltage limits

start to dominate. Although the above conclusion is the result of the analysis of the transconductor circuits of Fig. 4(c) and (d) (class A) as well as the transconductor circuits of Fig. 7(b) and (c) (class AB), we believe that it is generally true for any single-stage transconductor. Lineariza2) Review of Instantaneous Companding and tion Technique: Recently, there has been interest in a new family of current-mode lter topologies based upon so-called

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log-domain processing originally proposed by Adams [15]. The technique is particularly attractive since rst it is the large-signal transfer function of the lter that is linearized and not the individual transconductance elements as would be - based lters. Second, such the case in more classical linearization is based upon direct exploitation of the nonlinear characteristic of the device, in this case the p-n junction of a silicon diode. Furthermore Frey [10], [16] ingeniously showed that the large-signal characteristic of the bipolarjunction transistor (BJT) can be directly utilized to synthesize these log-domain lters by mapping from state-space linear differential equations. BJT technology is employed because of its unique exponential relationship, which is used as the state variable, together with the use of the well-known translinear circuit principle for global current transfer function linearization. Seevinck has also shown a BJT realization of this class of integrator, but referred to it as a companding integrator [11] based upon earlier work reported by Tsividis et al. [17]. In these integrators, companding describes the linearization mechanism in which signals are rst compressed to a intermediate integration node and then subsequently expanded (companding). Tsividis [18] has classied this group of integrators as belonging to the instantaneous companding integrators type. The denition instantaneous was used to distinguish between syllabic companding in the classical communication systems. Since a linear transconductance element cannot be elegantly realized by using exponential characteristics straightforwardly, then the instantaneous companding type lter is thus suitable for BJT, as well as weak inversion MOS, and this ties in well with the literature where most recent work has actually concentrated on this class [19][25]. Essentially log-domain integrators/lters exploit the fact that BJT technology can elegantly be employed to realize linear current transfer functions based upon translinear loops. However, we believe that if a linear transconductor can be - lter synthesis directly realized, the more classical methods should be employed and our analysis in the following sections would, therefore, be relevant. This seems to be particularly true for MOS realizations where in fact various techniques exist for transconductor linearization based on the square-law characteristic of FET [26][31]. 3) Transconductor Noise: Noise is another limitation on the dynamic range of the transconductor. Any transconductor can be represented as a noiseless device accompanied by equivalent noise sources (Fig. 9). Generally, the noise sources can be expressed as voltage and current noise (7) (8) where is Boltzmans constant and is absolute temperature and by neglecting noise generated by the biasing circuitry, the value of , the voltage noise factor and the current noise factor of the previous transconductors can be found in Table I. It can be seen from the above table that, in any case, is always much larger than . There are other kinds of

Fig. 9. Transconductor with equivalent noise sources.

Fig. 10. Voltage-mode

Gm -C

biquad lter.

TABLE I VOLTAGE NOISE FACTOR AND CURRENT NOISE FACTOR OF VARIOUS TRANSCONDUCTORS

transconductor which are and are not based on the above circuits. Most transconductors are developed to overcome the problem of nonlinearity and poor tunability. Although many of them are likely to conform to (7) and (8), some may not. However, for ease of analysis in the following sections, we will restrict our interest only in the transconductors that have equivalent noise sources that can be approximated by (7) and (8). B. Analysis of Voltage-Mode Filter

- biquad lter, equivaFig. 10 shows a voltage-mode lent to the circuit of Fig. 2(b). For convenience if the transconductance function of every transconductor is assumed frequency independent, i.e., , it can be shown that (9) (10)

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where

where if and

1) Signal Handling Capability versus Power Consumption Analysis: In this section, we will consider the relationship between the signal handling capability and power consumption - biquad lter. Since all nodal of the voltage-mode voltages and branch currents shown in the circuit of Fig. 10 can be expressed as a function of complex frequency the amplitude of these signals are thus varied with the frequency of the input signal and will reach a maximum value at a particular frequency. The maximum amplitude of these signals can be expressed as

if As an alternative to (13), can also be expressed as (14) where if if

if if

if if (11) where is the amplitude of the input voltage,

and

Note that (11) is derived from the assumption that all the transconductors exhibit innite bandwidth. However, (11) is still a good approximation in the more practical case where the bandwidth of each transconductor is much higher than . As discussed in Section II-A-1, to avoid excessive output signal distortion and amplitude-dependent effective transconductance, the ratio between the peak amplitude of output current and the bias current, , of each transconductor should of every transconductor in the circuit be kept small. If of Fig. 10 is assumed to be equal, the quiescent power consumption of the circuit, , can be expressed as (12) where is the level of supply voltage of the circuit. By using (9)(12), we obtain (13)

As discussed earlier, one can improve linearity of the transconductors by decreasing , however according to (13) and (14), the power consumption of the circuit will be increased. Thus the tradeoff between power consumption and linearity is evident. Also it can be seen from (13) and (14) that one can lower by reducing supply voltage, . However, is required to be high enough to guarantee that all the active devices in the transconductors are operating in the appropriate region. Later on, (13) and (14) will be used in determining the relationship between the quiescent power consumption and the dynamic range of the lter. 2) Noise Calculation: Fig. 11 shows the voltage-mode - biquad lter of Fig. 5 with the inclusion of equivalent input noise-voltage and noise-current generators for each transconductor. From the circuit of Fig. 11, with the input node grounded, by using (7) and (8) it can be shown that the total equivalent voltage output noise at nodes 1 and 2 is given by (15) where

and (16) where

It can be seen from (15) and (16) that the noise of the lter is inversely dependent on the value of the effective capacitor, , of the lter.

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Fig. 11.

Voltage-mode

Gm -C

biquad lter with noise sources.

3) Dynamic Range Consideration: Dynamic range of a circuit is dened as the ratio of the maximum and minimum signal level which the circuit can handle at the same time. The minimum signal level is determined by the noise of the circuit, the maximum level by distortion [32]. Mathematically, the dynamic range can be expressed as signal (17) DR noise is the magnitude of the output signal where signal when its THD reaches %. Regarding the low-pass output voltage, the dynamic range of the circuit of Fig. 10, DR , can be expressed as DR Combining (14), (16), and (18) yields DR (19) (18)

(23) where

and

1) Highest Signal Handling Capability versus Power Consumption Analysis: By following the procedure outlined in Section II-B-1, we nd that (24) where if

For the bandpass output voltage, the dynamic range of the circuit of Fig. 10, DR , can be expressed as if DR Combining (13), (15), and (20) we get (21) And clearly we see the interactive relationship between power, speed, and dynamic range. where if (20) or alternatively, (25)

C. Analysis of Current-Mode

Filter

if 2) Noise Calculation: Fig. 13 shows the current-mode - biquad lter of Fig. 12 with the inclusion of an equivalent input noise-voltage and noise current generators of each transconductor. So far, in the voltage-mode case, the transconductors are assumed to be frequency independent and the output noise is calculated by integrating the noise spectrum from zero

- biquad lter equivaFig. 12 shows a current-mode lent to the circuit of Fig. 3(b) where in [2], transconductors are of the type in Fig. 4(a). Again if the transconductors are assumed frequency independent, i.e., , it can be shown that (22)

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Fig. 12.

Current-mode

Gm -C

biquad lter.

Fig. 13.

Current-mode

Gm -C

biquad lter with noise sources.

to innity (excluding icker noise). However if the same is of the current-mode applied to the transconductor lter of Fig. 13, the total output noise currents contributed by would be innity. the noise source To avoid this, we need to limit the integrating frequency to a nite value. Also, in order to produce a more precise answer, should be included parasitic effects of the transconductor into the calculation. Yet this would make the noise calculation much more complicated. Hence in order to obtain a reasonable answer without introducing unnecessary complexity, the noise of Fig. 13 will spectral density of the noise sources inside yet lower than be integrated up to a frequency well above the frequency where stray parasitics take effect. where Hence by using (5) and (6), letting is the upper bound integrating frequency for the noise sources and assuming that in the frequency range below , inside is constant as a function of frequency, each noise source in it can be shown that the total noise currents of the circuit of Fig. 13 is given by (26)

where

and

(27)

where

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It can be seen from (26) and (27) that the output noise currents depend heavily on , the upper bound integrating frequency. Note that (26) and (27) are not valid for too high a value of , which is the case when not all noise sources inside are a constant function of frequency.

3) Dynamic Range Consideration: For the low-pass output can current of the circuit of Fig. 12, the dynamic range DR be expressed as DR (28)

if

if

if

if and according to (24)(27),

if

if

if

if

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FIGURE

OF

MERIT, F

OF

TABLE II VOLTAGE-MODE AND CURRENT-MODE

Gm -C FILTERS

DIMENSION

OF

MOSFET

AND

TABLE III BIAS CURRENTS USED IN

THE

SIMULATION

Combining (24), (26), and (28), we get DR

(29)

For the bandpass output current, the dynamic range of the circuit of Fig. 8, DR , can be expressed as DR Combining (25), (27), and (30) yields DR (30)

(31)

D. Comparison Between Voltage-Mode and Current-Mode Biquad Filter In order to compare the current-mode to voltage-mode biquad lter, each lter will be represented by an appropriate gure of merit, dened as DR (32) The gure of merit is simply a measurement of the efciency of the lter since it encapsulates the dynamic range which represents the range of signal levels for which the lter will perform properly, which represents the speed, and which is the power required by the lter to achieve such DR and . Thus by using (32) along with (19), (21), (29), and (31), Table II is constructed, where according to (13)(16), the equations and are shown at the bottom of the previous page. Fig. 14 shows an example of the contour plot of the ratio between the gure of merit of the currentmode over the voltage-mode biquad lter when , the ratio between the upper bound integrating frequency over , equals and are unity and assuming that 10, . It can be seen in Fig. 14(a) and (b) that, in both lowpass and band-pass cases, in the specied range of gain and , is always larger than which concludes that the voltage-mode - biquad is the higher performance design. E. Simulation Results In order to verify our analysis, the voltage-mode low-pass lter of Fig. 10 and the current-mode low-pass lter of Fig. 12 were simulated (using BNR 0.8 m BiCMOS technology parameters) and the results compared. In both circuits, pF were used and all the transconductor blocks are realized from the transconductor circuit of Fig. 4(d) (with one input node grounded) where the dimension of each MOS and the bias current of each transconductor block are chosen in a

way that of every transconductance block is equal. Table III shows the dimensions of each MOSFET and the bias current of each transconductor block. Both circuits are designed to have a second-order low-pass of 10 and of 3 MHz. characteristic with dc gain of 1, The simulation results of both circuits are shown in Fig. 15 and Table IV. The plots of Fig. 15 illustrate that the linearity of both types of simulated lters are effected by the ratio in the same way, i.e., when the ratio of both circuits are equal, they possess a comparable degree of linearity. It can also be shown that of both types of lters are the same, the when the ratio and , between both circuits voltage across capacitors, are also equal and hence the distortion of the output signals of both circuits are comparably dependent on the level of such voltages. This is an important observation since it suggests that, for the same level of output distortion, voltage swings across capacitors are the same for both current and voltage - topologies. mode lters based upon According to Table IV, the output noise of the voltage-mode lter is relatively the same whether the upper bound integration frequency is 30, 100, or 500 MHz. This stems from the fact that the magnitude response of all noise sources in such a circuit are shaped down at high frequency by the feedback mechanism. However, as seen from Table IV, this is not the case for the current-mode lter since the output transconductor of the circuit is not in the feedback loop and hence the magnitude response of its noise sources are not shaped down at high frequency by feedback. Table V shows the comparison between the calculated and where the simulated values of calculated values obtained from using Tables I and II and the simulated results from Table IV. As expected, as the upper integration frequency increases, is relatively more larger than . Also an error between the calculation and simulation results grows as the upper integration frequency increases. This stems from the fact that when the upper integration frequency is too high, our analysis of the noise of the current-mode lter will give a less precise answer (see Section II-C-2). F. Conclusion and Discussion We have performed an analysis on various aspects of - lter, namely, signal handling capacity, the biquad power consumption, noise, and dynamic range. Based on these properties, the gure of merit function has been developed and it is found to be heavily dependent on the value of gain and of the lter. As implied by the plots of Fig. 15, the voltage-mode lters of Fig. 10 and the current-mode lters of Fig. 12 possess a

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(a)

(b) Fig. 14. The contour plots of Fcurrent-mode =Fvoltage-mode of the Gm -C biquad lter: (a) low-pass: Fcurrent-mode =Fvoltage-mode 2 = 2 and (b) bandpass: Fcurrent-mode =Fvoltage-mode V V I I .

2 = V 2 V = I I

comparable degree of linearity when the ratio of both circuits are equal. This should also be true even in the extreme case when the signal clipping caused by the limited power supply voltage level occurs. Since, as mentioned in Section II-E, the distortion of the output signals of both circuits are comparably dependent on the level of the voltages across the integrating capacitors, then the clipping of these voltages would effect the distortion of the output signals of both types of circuits in a similar manner. Therefore, in general, the linearity of both circuits should still be relatively the same even when the clipping occurs. Consequently, although the argument within this paper is based upon the assumption that nonlinearity in the transconductance amplier is dominated by the magnitude

of the output current and its relationship to the bias current level and not by the voltage clipping induced by the limited power supply voltage, our argument should still be valid in the clipping case. It can be seen from Fig. 14 that, over a wide range of gain and , the voltage-mode lter outperforms its currentmode counterpart, at least in terms of our gure of merit. This stems largely from the fact that none of the equivalent noise sources of the transconductor employed in the voltagemode lter topology directly contributes to the output signal, i.e., the bandwidth of the output noise signal is shaped down by the lter topology. This is, however, not the case for the current-mode lter where the equivalent noise source of

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Fig. 15. The plots of  versus the simulated THD level of the output signals of the voltage-mode lter of Fig. 10 and the current-mode lter of Fig. 12 (the ratio  is varied by changing the level of the input signals).

TABLE IV SIMULATION RESULTS OF THE VOLTAGE-MODE FILTER OF FIG. 10 AND THE CURRENT-MODE FILTER OF FIG. 12

lter design similarly for both voltage-mode and current-mode lters. ACKNOWLEDGMENT The authors would like to acknowledge the referees of this paper who helped us improve the paper enormously. The authors would also like to thank Prof. Paul R. Gray of University of California, Berkeley, for his encouragement and valuable discussion. REFERENCES
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CALCULATED

AND

TABLE V SIMULATED VALUES OF Fcurrent-mode =Fvoltage-mode

its output transconductor directly contributes to the output signal. This should also be true in the case of the oscillators mentioned in Section II since, in a current-mode - oscillator, the oscillating output current is obtained by connecting a transconductor to the capacitor node and the noise source of this output transconductor also directly contributes to the output signal. In general the assumption has been that the linearity of the voltage-mode lter is the same as the current-mode. In the literature current-mode implementations actually use single nonlinear devices for the transconductor [2] and so the strength of this comparison is based upon classical voltage-mode - topology also using similar nonlinear transconductors. As such it is clear from this work that for the same linearity, voltage-mode lter processing would be the overall higher performance lter topology. Although this paper has been - based lter topology, in restricted to the more general theory the conclusion should apply to all realizations of based biquad lters, for instance the ones that employ multiple output OTA [2], [6] since such OTAs would simplify the

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Chris Toumazou (M87) is the Mahanakorn Professor of Analog Circuit Design in the Department of Electrical Engineering, Imperial College, London, England. He received the B.Sc. degree in engineering and the Ph.D. degree in electrical engineering from Oxford Brookes University, Oxford, England, in 1983 and 1986, respectively. Chris is a member of the IEE Professional Group E10 Committee on Circuits and Systems (U.K.) and was recently elected to the steering committee for the European NEAR program (Network for European Analogue Research). He is also a member of the Analog Signal Processing Committee of the IEEE Circuits and Systems Society for which he was Chairman (19921994) and is also Member of the Circuits and Systems Chapter of the U.K. and Republic of Ireland Section of the IEEE. Dr. Toumazou is a life member of the Electronics Society of Thailand. His research interests include current-mode analogue signal processing, high frequency, low power analogue integrated circuit design in bipolar CMOS and GaAs technology and Articial Intelligence applied to analogue circuit design. He is a co-winner of the IEE 1991 Rayleigh Best Book award for his part in editing Analog IC Design: The Current-Mode Approach and is also the recipient of the 1992 IEEE CAS Outstanding Young Author Award for his work with Dr. David Haigh on High Speed GaAs opamp design, as well as a co-winner of the 1995 IEE Electronics Letters Best Paper Premium Award. He has also edited and contributed several chapters to various books in the eld of analogue IC design, has authored or co-authored more than 180 technical publications in the area and holds four international patents. Dr. Toumazou is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, PART II. He was also recently elected as Vice-President for Technical Activities for IEEE Circuits and Systems Society.

Jirayuth Mahattanakul received the B.E. (electronics) degree from King Mongkuts Institute of Technology, Ladkrabang, Bangkok, Thailand, in 1990 and the M.Sc. degree in electrical engineering from Florida Institute of Technology, in 1992. From 1992 to 1994, he was a planning engineer for Telecom Asia Corp., Thailand. Since 1994, he has been with Mahanakorn University of Technology, Bangkok, Thailand and is currently working toward the Ph.D. degree at Imperial College of Science, Technology, and Medicine, London, U.K.