Application of Duality For Derivation of Current Converter Topologies
Application of Duality For Derivation of Current Converter Topologies
Application of Duality For Derivation of Current Converter Topologies
529-557
Copyright C 2005 Holon Academic Institute of Technology
Application of duality for derivation
of current converter topologies
Doron Shmilovitz
Faculty of Engineering, Tel-Aviv University,
Tel-Aviv 69978, Israel
e-mail: shmilo@eng.tau.ac.il
Received 1 April 2005, accepted 20 July 2005
Abstract
A unied approach is suggested for the derivation of current-to-
current converter topologies, which relies on duality principles. As
conventional duality rules have restricted utility and are dicult to ap-
ply with switched mode circuits, special attention is devoted to switch
mode converter element dualities. Also, a special means of viewing
complex switched mode topologies as a cascade combination of building
blocks is developed. This method simplies the treatment of circuits
containing transformers and switching bridges.
The suggested approach provides a universal means for derivation of
current-to-current converters by dually transforming voltage-to-voltage
converter topologies.
Examples of the utilization of this method for derivation of vari-
ous current-to-current converters, including Buck, Boost, Buck-Boost,
1 s = 1
1 s = 2
(8)
as depicted in Fig. 7.
Figure 7: The virtual variable transformer model of the switching bridge
and its dual.
Since k is either 1 or (-1), the virtual transformer maps into a virtual
transformer with the same instantaneous turns ratio (4). This inverting
switching bridge is thus invariant to dual transformation. To ensure practical
operation, duality should be applied not only to circuit elements but also to
switching functions. If, for instance, a in Fig. 7 is a voltage source, a dead
time must be implemented in the switching bridge in order to prevent shoot-
through currents. Whereas, in the dual circuit (Fig. 7b), a
D
is a current
source, and an overlapping of the on states will automatically result by
application of duality to the switching function, ensuring current continuity.
Switching bridges are often employed in power converters in conjunction
with a transformer to form an alternating signal at the transformers input.
This is actually a cascade connection of two two-port-elements (Fig. 8).
Applying the duality rule for cascade connection successively (for each TPE)
would result in a similar cascade topology in which each of the networks in
each of the two two-port-elements is replaced by its dual element, see Fig. 8.
That is correct in principle, however, details of implementation like those
mentioned above must be considered. Similarly, switching bridges that gen-
erate zero levels in addition to their input or inversed input, can be treated
by analyzing their functionality rather than by the straightforward applica-
tion of duality. For instance, a three level voltage source inverter generates
at the bridge output a waveform as shown in Fig. 9 where x = z and y = w
in order to prevent a short across V
G
.
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Figure 8: A cascade connection of two two-port-elements and its dual.
Figure 9: A three level inverter (a) and its output voltage waveform (b).
The varying turns ratio transformer approach cannot be employed in
this case since it would involve a turns ratio of either 0 or . In the dual
circuit, a current source should appear at the b-b terminals which has the
precisely same waveform as the voltage in the original circuit (Fig. 9b). This
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would be accomplished by replacing the voltage source V
G
with a current
source I
G
and exercising the bridge switches dierently, as shown in Fig. 10.
The new sequence would be: x, w x, z y, z and y, w. In
this dual circuit x = y and z = w in order to ensure always a closed path
for I
G
. This approach can serve for the development of various topologies
involving switching bridges, such as current source inverters or unity power
factor rectiers, which practically implement a sinusoidal current source with
respect to the AC mains.
Figure 10: The three level inverter (a) and its output current waveform (b).
3 Derivation of some current-to-current converter
topologies
Development of current-to-current converter topologies can be either done
from scratch or accomplished by applying some symmetry principles such as
horizontally ipping of portions of a voltage converter [4] or by manipulation
of a switched capacitor cell [5]. While doing so, some basic requirements
must be ensured:
the converter topology must always provide a current path for the
input current source, regardless of the switches states;
no inductor may connect to the input;
output parameters (current or voltage) should be controllable via a
switching parameter such as the duty ratio, D.
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Figure 11: Successive application of the method for a buck topology.
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Additionally, the system must be stable under dynamical conditions.
When deriving a current-to-current converter topology via the duality method
proposed herein, the above mentioned requirements are automatically ful-
lled, without special care. Moreover, the same DC voltage gain that applied
for the original converter V
O
/V
G
should be valid for the DC current gain
I
O
/I
G
of the dual converter. Applying the duality rules stated in the previ-
ous paragraph, yields some current-to-current converter topologies. Herein
are some examples. Consider the voltage buck converter represented by
three branches, a, b, and c, as in Figs. 11a and 11b. The original circuits
graph is depicted in Fig. 11b. Since these branches are connected in parallel,
the graph maps into its dual as shown in Fig. 11c. Branch a consists of two
branches a
1
and a
2
connected in series, which maps therefore as a parallel
connection of the dual branches a
D
1
and a
D
2
(Fig. 11d). Similarly, branch c
consists of two branches c
1
and c
2
connected in series, which map into a
parallel connection of their duals c
D
1
and c
D
2
, as shown in Fig. 11e. c
2
itself
consists of two branches c
21
and c
22
which maps into c
D
2
according to the
same rules (Fig. 11f).
Figure 12: Graph transformation of the buck topology: (a) original circuit;
(b) dual transformation.
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The graph of the original buck topology can now be represented in terms
of basic branches by substitution of each subgraph in the place of the equiv-
alent graph, as shown in Fig. 12a. Performing the same substitution process
for the dual sub graphs results in the total dual graph as depicted in Fig.
12b.
In this last graph, each branch is composed of a single network element,
which means that each branch can be replaced by the dual network element
according to the network elements transformations shown in Fig. 3, resulting
in the dual converter topology depicted in Fig. 13.
Figure 13: The resulting dual buck topology.
Regardless of component values, the current-to-current topology has
been derived, as shown in Fig. 14. It will be shown that it has the DC
gain of a buck topology with respect to output to input current ratio.
Figure 14: Buck current to current converter.
Similarly, the conventional boost voltage-to-voltage topology and its
graph description are shown in Fig. 15. The dual of this graph is derived
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via the duality graph transformation rules (Fig. 16a), and nally replace-
ment of each branch by the suitable dual component results in the boost
current-to-current converter topology depicted in Fig. 16b.
Figure 15: A voltage boost topology (a) and its graph representation (b).
Figure 16: Dual boost derivation: (a) graph transformation; (b) component
placement.
A buck-boost voltage-to-voltage topology and its branch assignment are
shown in Fig. 17. It may be observed by inspection that this topology is
described by the same graph as the boost converter (Fig. 15b), thus the
resulting dual graph is also the same (Fig. 16a).
Finally, the buck-boost current-to-current converter topology is obtained
by placing the suitable component duals, see Fig. 18 (it may be noted that
the only dierence with respect to the boost topology arises from substitu-
tion of components for branches a
2
and b).
Higher order current-to-current converter topologies can be derived
through the same method as well. For instance, when continuous wave-
forms are desired at the source terminal as well as at the load terminal, a
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boost-buck (
0 s = 1
v
c
(t) i
g
(t) s = 0
. (9)
The average lter input current over a switching period is derived:
hi
f
(t)i
T
S
= h(1 d (t)) i
g
(t)i
T
S
. (10)
Since the input current hardly changes during a switching period and
the duty ratio is actually dened as the on time during a switching period,
equation (8) can be simplied:
hi
f
(t)i
T
S
= (1 d (t)) i
g
(t) . (11)
With appropriate lter components, the ripple component of i
f
ows
through the capacitor while the DC component ows through the inductor
and the load. The DC transfer function is derived:
V
o
= (1 D) I R
l
. (12)
Equation (12) shows that the load voltage is controllable via the duty
ratio and thus the topology complies with the requirement no. 3. However,
(12) also indicates that unlike as in conventional switched mode converters,
the output voltage is inherently load dependent, thus output regulation is
possible only with a closed loop mode. It can be seen from Fig. 23 that
a pulsating current i
f
is injected at the capacitor-inductor junction. As
long as the capacitor presents an impedance, that is much lower than the
inductor and load series combination, all of the current AC components may
be assumed to ow through the capacitor while the current average ows
through the inductor and load. Thus the capacitor current is a square wave
with a peak-to-peak amplitude equal to that of the source i
g
and zero DC
component, see Fig. 24.
The resulting capacitor voltage ripple can be formulated as
v
c
=
d (1 d) I
g
2 f
S
C
. (13)
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Figure 24: Main waveforms in the converter. Top to bottom: lter input
current, capacitor current, and capacitor voltage ripple.
The maximum capacitor voltage ripple is:
v
c
=
I
g
8 f
S
C
. (14)
Not all of this ripple develops on the load; there is an additional ripple
reduction due to the inductor impedance. The maximum output ripple can
be approximated as:
v
loadmax
=
Z
load
()
Z
load
() + jL
I
g
8 f
S
C
. (15)
These expressions can serve for the selection of capacitor, inductor, and
switching frequency according to the allowable ripple.
4.2 Power manipulation and SMES coil current decay prole
With given load, regulation of the output voltage means supplying a con-
stant output power. Assuming low losses within the converter, this means a
steady power throughput and a constant decrease of the energy stored in the
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superconducting coil reservoir. The energy stored in the superconducting
coil and the rate of discharge are
E
SMES
=
L
SMES
i
g
(t)
2
2
;
d
dt
(E
SMES
) = p
out
=
V
2
load
R
load
. (16)
which yields the superconducting coil current:
i
g
(t) =
r
i
g
(0)
2
2 P t
L
SMES
=
s
i
g
(0)
2
2 V
2
load
t
L
SMES
R
load
. (17)
The duty ratio variation over the discharge time is found by substituting
(17) into (11).
d (t) = 1
V
load
q
i
g
(0)
2
2Pt
L
SMES
R
load
= 1
V
load
q
i
g
(0)
2
R
2
load
2V
2
load
R
load
t
L
SMES
(18)
which indicates that output regulation is lost at t
cr
, shortly before all the
stored energy is exhausted.
t
cr
=
1
2
i
g
(0) L
SMES
R
l
V
2
l
L
SMES
R
l
. (19)
These equations are in agreement with the SPISE simulation results
shown in the next section.
4.3 Small signal analysis
Figure 25 shows a low-frequency model of the proposed converter in which
the switching network was replaced by two dependent sources.
Figure 25: Low frequency AC model of the converter.
Accounting to frequencies much lower than the switching frequency [1],
this model provides a fair approximation for both large and small signals.
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For the small signal analysis an averaged switch network replaces the switch,
which is equivalent to perturbation and linearization process [1], see Fig. 26.
Figure 26: Averaged switch model (a) and the converter small signal
model (b).
In addition, the model was augmented by the equivalent series resistance
(ESR) of the capacitor, r
C
. Modeling of the inductor resistance is not needed
since it is included in the load resistance. After some circuit manipulation,
a simplied model which models the small signal behavior is reached and
shown in Fig. 26b. This model has a simple transfer function with two poles
and one zero in the LHP.
v
load
=
r
C
R
load
D
0
d
0
L
S +
1
r
C
C
S
2
+
r
C
+R
load
L
S +
1
LC
i
g
. (20)
As it can be observed, this topology is unconditionally stable for duty
ratios in the range of 01.
4.4 Simulation and experimental results
The circuit is meant to connect to a UPS DC bus at its output, therefore
the converter output is regulated at 400 Volt. The power stage linearized
transfer function (19) was employed for the derivation of the controller.
551
Figure 27: The average model simulation scheme.
Figure 28: The average model simulation results.
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The circuit was simulated by SPICE software, rst with averaged models
and later using switching models. The average model is shown in Fig. 27,
the focus is on the converter section while the rest of the scheme is about
charging and protecting the SMES coil.
The SMES coil is assumed to have an inductance of 0.5H and be initially
charged to almost 50A. The average mode simulation results are shown in
Fig. 28.
The satisfactory load voltage regulation can be noticed as well as the
duty ratio and current variation, in accordance with (17) and (18). For the
switching detailed simulation, a switching circuit with realistic component
models replaced the average model of Fig. 28. A simple voltage mode
modulator was incorporated. The output is well regulated until all the
superconductor energy is exhausted (at t 86ms). The parabolic prole of
current decrease may be noticed, in accordance with (17) and (18) and with
the average model simulation, see Fig. 29.
Figure 29: Converter input voltage (ch1 20V/div), and input current (ch2
2A/div).
Experimental results are presented for a partial loading of 110 Watt,
down sized prototype. In the experimental setup a 470F capacitor and
20H inductor were used and the switching frequency was 70kHz. The
input current I
G
is 4A. The output is regulated at 50V and the load is a
22 resistor. Typical waveforms are presented in Fig. 30.
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Figure 30: Simulation results in the switched mode.
Figure 31: Experimental steady state transfer ratio of the dual buck at
I
g
= 4A.
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The steady state transfer ratio from input current to output voltage
is shown in Fig. 31, which agrees with (12). Due to simplicity and low
component count, high eciency is achieved even with hard switching, see
Fig. 31.
A dual buck-boost current converter was build and tested at the same
power level as well.
Comparison between theoretical and experimental results is provided in
Fig. 32.
Figure 32: Experimental steady state transfer ratio of the dual buck-boost
converter at I
g
= 4A.
5 Conclusions
A unied approach for the derivation of current-to-current converter topolo-
gies was presented. In this method, previously known duality principles
are augmented by the application of cascaded two port elements and func-
tional analysis of circuits, as well as by the successive application of se-
ries/parallel transformation. Switching bridges are modeled by a virtual
variable-transformer, which greatly simplies the treatment of circuits con-
taining transformers and switching bridges. Thus, a universal tool for
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derivation of current-to-current converters by dually transforming voltage-
to-voltage converter topologies was developed. Some examples for the ap-
plication of this method show its consistency.
Experimental results for a practical design of a current-to-current con-
verter for SMES (Superconducting Magnetic Energy Storage) application
were also provided.
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