74hc11d Porte Et 3 Entrees

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Product specication

File under Integrated Circuits, IC06


December 1990
INTEGRATED CIRCUITS
74HC/HCT11
Triple 3-input AND gate
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specication
Triple 3-input AND gate 74HC/HCT11
FEATURES
Output capability: standard
I
CC
category: SSI
GENERAL DESCRIPTION
The 74HC/HCT11 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT11 provide the 3-input AND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
= C
PD
V
CC
2
f
i
+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
(C
L
V
CC
2
f
o
) = sum of outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
ORDERING INFORMATION
See 74HC/HCT/HCU/HCMOS Logic Package Information.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay nA, nB, nC to nY C
L
= 15 pF; V
CC
= 5 V 10 11 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per gate notes 1 and 2 18 20 pF
December 1990 3
Philips Semiconductors Product specication
Triple 3-input AND gate 74HC/HCT11
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 3, 9 1A to 3A data inputs
2, 4, 10 1B to 3B data inputs
7 GND ground (0 V)
12, 6, 8 1Y to 3Y data outputs
13, 5, 11 1C to 3C data inputs
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Fig.4 Functional diagram. Fig.5 Logic diagram (one gate).
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
INPUTS OUTPUT
nA nB nC nY
L L L L
L L H L
L H L L
L H H L
H L L L
H L H L
H H L L
H H H H
December 1990 4
Philips Semiconductors Product specication
Triple 3-input AND gate 74HC/HCT11
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications.
Output capability: standard
I
CC
category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL PARAMETER
T
amb
(C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS +25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA, nB, nC to nY
32 100 125 150 ns 2.0 Fig.6
12 20 25 30 4.5
10 17 21 26 6.0
t
THL
/ t
TLH
output transition
times
19 75 95 110 ns 2.0 Fig.6
7 15 19 22 4.5
6 13 16 19 6.0
December 1990 5
Philips Semiconductors Product specication
Triple 3-input AND gate 74HC/HCT11
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications.
Output capability: standard
I
CC
category: SSI
Note to HCT types
The value of additional quiescent supply current (I
CC
) for a unit load of 1 is given in the family specifications.
To determine I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
AC WAVEFORMS
PACKAGE OUTLINES
See 74HC/HCT/HCU/HCMOS Logic Package Outlines.
INPUT UNIT LOAD COEFFICIENT
nA, nB, nC 1.00
SYMBOL PARAMETER
T
amb
(C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS +25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA, nB, nC to nY
16 24 30 36 ns 4.5 Fig.6
t
THL
/ t
TLH
output transition
times
7 15 19 22 ns 4.5 Fig.6
Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition
times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

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