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Combinational Gate Design

CMOS Combinational Gate Design discusses compound gates, input order, symmetric and asymmetric gates, skewed gates, and dynamic logic gates. Some key points include: 1) Compound gates can have lower delay than an equivalent simple gate design using fewer transistors. Input order affects parasitic delay, with the latest input minimizing delay. 2) Skewed gates favor one input or transition over another to reduce delay. A catalog of skewed gates shows their logical effort values. 3) Dynamic logic gates use a precharge phase and evaluation phase to produce monotonic outputs but require monotonically rising inputs during evaluation. Domino gates add an inverting static gate to ensure monotonic outputs.

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Nowshin Alam
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66 views25 pages

Combinational Gate Design

CMOS Combinational Gate Design discusses compound gates, input order, symmetric and asymmetric gates, skewed gates, and dynamic logic gates. Some key points include: 1) Compound gates can have lower delay than an equivalent simple gate design using fewer transistors. Input order affects parasitic delay, with the latest input minimizing delay. 2) Skewed gates favor one input or transition over another to reduce delay. A catalog of skewed gates shows their logical effort values. 3) Dynamic logic gates use a precharge phase and evaluation phase to produce monotonic outputs but require monotonically rising inputs during evaluation. Domino gates add an inverting static gate to ensure monotonic outputs.

Uploaded by

Nowshin Alam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CMOS Combinational Gate Design

(Chapter 9)
Bharadwaj Amrutur
ECE Dept !!S" Bangalore #$
2
Compound gates
3
Compound %ersus Simple Gates
Using Simple Gates:
G =
P =
4
Compound %ersus Simple Gates
Using Simple Gates:
G = 5/3 * 4/3 * 5/3 = 100/27 = 3.7
P = 2 + 1 + 2 + 1 + 2 = 8
Delay = 3.7 * + 8
!"# $"mp"%n& Gate
Delay = 2.7 + 5.4
5
!nput Order

Cal"ulate parasiti" dela& 'or ( 'alling


) !' A arri*es last+
) !' B arri*es last+
6C
2C
2
2
2 2
B
A
x
Y
'
!nput Order

Cal"ulate parasiti" dela& 'or ( 'alling


) !' A arri*es last+
, B-#-.node / is alread& at 01 So dis"harge
time"onstant o' ( - (2 3 2) 4 5C - 5C
) !' B arri*es last+
, A-#-. node / is %dd6%t1 Both / and & ha*e to be
dis"harged -. time"onstant - 2 ($C35C) 3 2 (5C) -
7C1
6C
2C
2
2
2 2
B
A
x
Y
7
!nner 8 Outer !nputs

!' input arri*al time is 9nown


, Conne"t latest input to inner terminal
2
2
2 2
B
A
Y
8
S&mmetri" Gates

!nputs "an be made per'e"tl& s&mmetri"


A
B
Y
2
1
1
2
1
1
6C
2C
2
2
2 2
B
A
x
Y
(
As&mmetri" Gates

As&mmetri" gates 'a*or one


input o*er another

E/: suppose input A o' a ;A;D


gate is most "riti"al

<se smaller transistor on A


(less "apa"itan"e)

Boost si=e o' non"riti"al


input

So total resistan"e is same

g
A
- #0>9

g
B
- $

As&mmetri" gate approa"hes g


- # on "riti"al input when other
transistors are made *er& large
10
?igh Speed Digital Cir"uit Design

@otal e''ort A - G B ?

?igh speed -. lower A

? and B are ultimatel& determined b& mi"ro6


ar"hite"ture

G is determined b& logi" and "ir"uit design


, Choose low G gates
, Change "ir"uit topolog& to redu"e G 'or a gi*en
gate1 ?ow+
11
S9ewed Gates

S9ewed gates 'a*or one edge o*er another

E/: suppose rising output o' in*erter is most "riti"al

Downsi=e non"riti"al nMOS transistor

Cal"ulate logi"al e''ort b& "omparing to uns9ewed in*erter with


same e''e"ti*e resistan"e on that edge1

g
u
-

g
d
-
1/2
2
A Y
1
2
A Y
1/2
1
A Y
HI-skew
inverter
unskewed inverter
(equal rise resistance)
unskewed inverter
(equal fall resistance)
12
S9ewed Gates

S9ewed gates 'a*or one edge o*er another

E/: suppose rising output o' in*erter is most "riti"al

Downsi=e non"riti"al nMOS transistor

Cal"ulate logi"al e''ort b& "omparing to uns9ewed in*erter with


same e''e"ti*e resistan"e on that edge1

g
u
- $1B>C - B>5

g
d
- $1B>#1B - B>C
1/2
2
A Y
1
2
A Y
1/2
1
A Y
HI-skew
inverter
unskewed inverter
(equal rise resistance)
unskewed inverter
(equal fall resistance)
13
?!6 and DO6S9ew

De': Dogi"al e''ort o' a s9ewed gate 'or a parti"ular


transition is:

the ratio o' the input "apa"itan"e o' that gate to


the input "apa"itan"e o' an uns9ewed in*erter
deli*ering the same output "urrent 'or the same
transition1

S9ewed gates redu"e si=e o' non"riti"al transistors

?!6s9ew gates 'a*or rising output (small nMOS)

DO6s9ew gates 'a*or 'alling output (small pMOS)

Dogi"al e''ort is smaller 'or 'a*ored dire"tion

But larger 'or the other dire"tion


14
Catalog o' S9ewed Gates
1/2
2
A Y
Inverter
1
1
2 2
B
A
Y
B
A
A!2 "#2
1/2 1/2
$
$
HI-skew
%"-skew
1
1
A Y
2
2
1 1
B
A
Y
B
A
1 1
2
2
&
u
' (/6
&
d
' (/)
&
av&
' (/$
&
u
' $/)
&
d
' 2/)
&
av&
' 1
&
u
' 1
&
d
' 2
&
av&
' )/2
&
u
' 2
&
d
' 1
&
av&
' )/2
&
u
' )/2
&
d
' )
&
av&
' */$
&
u
' 2
&
d
' 1
&
av&
' )/2
Y
Y
1
2
A Y
2
2
2 2
B
A
Y
B
A
1 1
$
$
unskewed
&
u
' 1
&
d
' 1
&
av&
' 1
&
u
' $/)
&
d
' $/)
&
av&
' $/)
&
u
' (/)
&
d
' (/)
&
av&
' (/)
Y
15
As&mmetri" S9ew

Combine as&mmetri" and s9ewed gates


, Downsi=e non"riti"al transistor on unimportant input
, Eedu"es parasiti" dela& 'or "riti"al input
A
reset
Y
$
$/)
2 1
reset
A
Y
1'
E/treme s9ewing

DonFt dri*e the pullup (or pulldown) at all

?ow to restore logi" le*el a'ter a pulldown e*ent+


, Alwa&s on pullup de*i"e: Gseudo nMOS
, Gre"harge transistor: D&nami" "ir"uits1

Gseudo6nMOS

!n the old da&s nMOS pro"esses had no pMOS

!nstead use pull6up transistor that is alwa&s O;

!n CMOS use a pMOS that is alwa&s O;

Eatio issue

Ma9e pMOS about H e''e"ti*e strength o' pulldown


networ9
+
,ut
+
in
16/2
-/2
I
ds
l,ad
. ./) ./6 ./* 1/2 1/( 1/0
.
./)
./6
./*
1/2
1/(
1/0
- ' 2$
- ' $
- ' 1$
+
in
+
,ut

Gseudo6nMOS Gates

Design 'or unit "urrent on output to "ompare with unit


in*erter1

pMOS 'ights nMOS


Inverter A!2 "#2
$/)
2/)
A
Y
0/)
0/)
2/)
B
A
Y
A B
$/) $/)
2/)
&
u
' $/)
&
d
' $/*
&
av&
' 0/*
1
u
' 6/)
1
d
' 6/*
1
av&
' 12/*
Y
&
u
' 0/)
&
d
' 0/*
&
av&
' 16/*
1
u
' 1./)
1
d
' 1./*
1
av&
' 2./*
&
u
' $/)
&
d
' $/*
&
av&
' 0/*
1
u
' 1./)
1
d
' 1./*
1
av&
' 2./*
f
in1uts
Y

Gseudo6nMOS Gower

Gseudo6nMOS draws power whene*er ( - 0

Called stati" power G - !)%


DD

A 'ew mA > gate 4 #M gates would be a problem

@his is wh& nMOS went e/tin"tI

But re6e/amine in "onte/t o' high subthreshold lea9age1

<se pseudo6nMOS sparingl& 'or wide ;OEs

@urn o'' pMOS when not in use


A B
Y
C
en

D&nami" Dogi"

D&nami" gates uses a "lo"9ed pMOS pullup

@wo modes: pre"harge and e*aluate


1
2
A Y
$/)
2/)
A
Y
1
1
A
Y

2tatic -seud,-n3"2 !4na5ic


-rec6ar&e 7valuate
Y
-rec6ar&e

@he Aooter

Jhat i' pulldown networ9 is O; during pre"harge+

<se series e*aluation transistor to pre*ent 'ight1


A
Y

f,,t
1rec6ar&e transist,r

Y
in1uts

Y
in1uts
f,,ted unf,,ted
f f

Dogi"al E''ort
Inverter A!2 "#2
1
1
A
Y
2
2
1
B
A
Y
A B
1 1
1
&
d
' 1/)
1
d
' 2/)
&
d
' 2/)
1
d
' )/)
&
d
' 1/)
1
d
' )/)
Y

2
1
A
Y
)
)
1
B
A
Y
A B
2 2
1
&
d
' 2/)
1
d
' )/)
&
d
' )/)
1
d
' $/)
&
d
' 2/)
1
d
' (/)
Y

f,,ted
unf,,ted
)
2
2

Monotoni"it&

D&nami" gates reKuire monotoni"all& rising inputs during


e*aluation

0 6. 0

0 6. #

# 6. #

But not # 6. 0
-rec6ar&e 7valuate
Y
-rec6ar&e
A
"ut1ut s6,uld rise 8ut d,es n,t
vi,lates 5,n,t,nicit4
durin& evaluati,n
A


Monotoni"it& !ssues

But d&nami" gates produ"e monotoni"all& 'alling


outputs during e*aluation

!llegal 'or one d&nami" gate to dri*e anotherI


A
9

Y
-rec6ar&e 7valuate
9
-rec6ar&e
A ' 1
Y s6,uld rise 8ut cann,t
Y
9 5,n,t,nicall4 falls durin& evaluati,n

Domino Gates

Aollow d&nami" stage with in*erting stati" gate

D&nami" > stati" pair is "alled domino gate

Grodu"es monotoni" outputs


-rec6ar&e 7valuate
:
-rec6ar&e
9
Y
;
A

B
C

C
A
B
: 9
Y
;
'
9
;
H
H
A
:

B C
9 Y ;
d,5in, A!
d4na5ic
A!
static
inverter

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