UT Austin, ECE Department

VLSI Design
7. Combinational Circuits

Example 1
7. Combinational Circuits module mux(input s, d0, d1,
output y);
• Last module:
– Delay in logic networks assign y = s ? d1 : d0;
endmodule
– Logical Effort
– Choosing the best number of stages 1) Sketch a design using AND, OR, and NOT
• This module: gates.
D0
– Designing CMOS gate networks S
– Speeding up combinational gates Y
D1
S

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Example 2 Bubble Pushing

2) Sketch a design using NAND, NOR, and • Start with network of AND / OR gates
NOT gates. Assume ~S is available. • Convert to NAND / NOR + inverters
• Push bubbles around to simplify logic
– Use DeMorgan’s Law

Y Y

(a) (b)

Y Y

D
(c) (d)

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Example 3 Compound Gates

• Logical Effort of compound gates
3) Sketch a design using one compound gate
unit inverter AOI21 AOI22 Complex AOI
and one NOT gate. Assume ~S is available. Y=A Y = A B+C Y = A B+C D Y = A (B + C) + D E
D
A A E
Y
B B A
A Y Y Y
C C B
D C

A 4 B 4 A 4 B 4 B 6
D0 A
2
Y
C 4
Y
C 4 D 4
Y
C 6 A 3

S 1 A 2
C 1
A 2 C 2 D 6 E 6
Y
Y B 2 B 2 D 2 E 2 A 2

D1 D 2 B 2 C 2

S gA = 3/3
p = 3/3
gA = 6/3
gB = 6/3
gA = 6/3
gB = 6/3
gA = 5/3
gB = 8/3
gC = 5/3 gC = 6/3 gC = 8/3
p = 7/3 gD = 6/3 gD = 8/3
p = 12/3 gE = 8/3
p = 16/3

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UT Austin, ECE Department
VLSI Design
7. Combinational Circuits

Example 4 NAND Solution

• The multiplexer has a maximum input
capacitance of 16 units on each input. It P =2+2= 4 D0
must drive a load of 160 units. Estimate the G = (4 / 3) (4 / 3) = 16 / 9
S
Y
delay of the NAND and compound gate D1
F = GBH = 160 / 9 S
designs.
fˆ = N F = 4.2
D0 D0
D = Nfˆ + P = 12.4τ
S S
Y Y
D1
D1
S S

H = 160 / 16 = 10
B=1
N=2
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Compound Solution Example 5

• Annotate your designs with transistor sizes
P = 4 +1 = 5 D0
that achieve this delay.
G = (6 / 3) (1) = 2 S
D1
Y
8 8
F = GBH = 20 S
8 10 10
8 25 25 10 10 24
fˆ = N F = 4.5 Y Y
25 6 6 12
D = Nfˆ + P = 14τ 8 8 25 6 6
8
8
16 160 * (4/3) / 4.2 = 50 16 160 * 1 / 4.5 = 36

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Input Order Inner & Outer Inputs

• Our parasitic delay model was too simple • Inner input is closest to output (A)
– Calculate parasitic delay for Y falling • Outer input is closest to rail (B)
• If A arrives latest? 2τ
• If B arrives latest? 2.33τ 2 2 Y
A 2
2 2 Y B 2
A 2 6C

B 2x 2C
• If input arrival time is known
– Connect latest input to inner terminal
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UT Austin, ECE Department
VLSI Design
7. Combinational Circuits

Asymmetric Gates Symmetric Gates

• Asymmetric gates favor one input over another
• Inputs can be made perfectly symmetric
• Example: Suppose input A of a NAND gate is most
critical
– Use smaller transistor on A (less capacitance)
– Boost size of noncritical input A
2 2
– So total resistance is same reset
Y Y
A 1 1
• gA = 10/9 2 2

• gB = 2
Y
B 1 1
A 4/3
reset 4
• gtotal = gA + gB = 28/9
• Asymmetric gate approaches g = 1 on critical input
• But total logical effort goes up
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Skewed Gates HI- and LO-Skew

• Skewed gates favor one edge over another • Logical effort of a skewed gate for a particular
• Ex: suppose rising output of inverter is most transition is the ratio of the input capacitance of
critical that gate to the input capacitance of an unskewed
– Downsize noncritical nMOS transistor inverter delivering the same output current for the
HI-skew
inverter
unskewed inverter
(equal rise resistance)
unskewed inverter
(equal fall resistance)
same transition
2 2 1 • Skewed gates reduce size of noncritical
A Y A Y A Y
1/2 1 1/2 transistors
– HI-skew gates favor rising output (small nMOS)
• Calculate logical effort by comparing to unskewed
– LO-skew gates favor falling output (small pMOS)
inverter with same effective resistance on that
edge. • Logical effort is smaller for favored direction
– gu = 2.5 / 3 = 5/6 • But larger for the other direction
– gd = 2.5 / 1.5 = 5/3
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Catalog of Skewed Gates Asymmetric Skew

Inverter NAND2 NOR2 • Combine asymmetric and skewed gates
2 2 B 4
– Downsize noncritical transistor on unimportant
2 A 2
Y
A 4 input
unskewed A Y Y
1 2 1 1
gu = 1
gd = 1
B gu = 4/3
gd = 4/3
gu = 5/3
gd = 5/3
– Reduces parasitic delay for critical input
gavg = 1 gavg = 4/3 gavg = 5/3
2 4
2 B A
2
Y
A 4 Y
HI-skew A Y
A 1
Y reset
1/2 g = 5/6 B 1 gu = 1 1/2 1/2 gu = 3/2
u
gd = 5/3 gd = 2 gd = 3
gavg = 5/4 gavg = 3/2 gavg = 9/4
1 1 B 2 1 2
Y
Y
1 A 2
A 2
LO-skew A Y Y A 4/3
1 gu = 4/3 B 2 gu = 2 1 1 gu = 2
gd = 2/3 gd = 1 gd = 1 reset 4
gavg = 1 gavg = 3/2 gavg = 3/2

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UT Austin, ECE Department
VLSI Design
7. Combinational Circuits

Best P/N Ratio for Least Avg Delay P/N Ratios

• In general, best P/N ratio for lowest avg delay is
• We have selected P/N ratio for unit rise and
fall resistance (μ = 2-3 for an inverter). the square root of that giving equal delay
– Only improves average delay slightly for inverters
• Alternative: ratio for least average delay
– But significantly decreases area and power for NOR
• Ex: inverter Inverter NAND2 NOR2
– Delay driving identical inverter P
A
2
– tpdf = (P+1) 1 2 2
Y
B
2
fastest A
1.414
Y
A 2
A
Y
– tpdr = (P+1)(μ/P) P/N ratio 1 gu = 1.15 B 2 gu = 4/3 1 1 gu = 2

– tpd = (P+1)(1+μ/P)/2 = (P + 1 + μ + μ/P)/2

gd = 0.81 gd = 4/3 gd = 1
gavg = 0.98 gavg = 4/3 gavg = 3/2

– Differentiate tpd w.r.t. P • In practice, P/N ratio consideration not really

– Least delay for P = μ average delay
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