Amity School of Engineering & Technology Digital Circuits & System - Ii Tutorial No. - 1

AMITY SCHOOL OF ENGINEERING & TECHNOLOGY
DIGITAL CIRCUITS & SYSTEM II (BTE 501)

TUTORIAL NO. 1
Q. 1) Define the following:
(a) clock period (b) clock frequency (c) clock width (d) duty cycle
Q. 2) Derive the state table and state diagra for (1) !" #lip #lop (2) $% #lip #lop (2) &
#lip #lop (') D #lip #lop. (lso give the characteristics equation and e)citation table
for the above ##*s.
Q. +) ( sequential circuit with two D flip flops ( to , - two inputs ) and y- and one output .
is specified by the following ne)t state and output equation.
- ) 1 ( xA y x t A + = +
B z xA B x t B = + = + - ) 1 (
a) Draw the logic diagra of the circuit.
b) Derive the state table.
c) Derive the state diagra
Q. ') ( sequential circuit has one #lip #lop/ Q- two inputs ) and y - one outputs s. 0t
consists of a full adder circuit connected to a D##/ as shown on figure 11. Derive
state table and state diagra of the sequential circuit.
figure 11
Q. 2) Derive state table and state diagra for the sequential circuit given in figure 12.
figure 12
1
Full
Adde
!
D
Cl"#$
S %
&
!
C
Full
Adde
!
D
Cl"#$
S %
&
!
C
B
A
A'
!' !
A
T
B'
!' !
B
T
Cl"#$
B
A
A'
!' !
A
T
B'
!' !
B
T
Cl"#$
Q. 3) ( sequential circuit has two $%/ #lip flops one input )/ one output y as shown in
figure 1 + Derive the state table and state diagra.
figure 1 +
Q.4)(a) 5onstruct a state table and graph for the given network (b) 5onstruct a tiing chart
for the network for an input sequence ) 6 17711. 0ndicate at what ties 8 has the
correct value and specify the correct sequence ((ssue that e)changes id way
between clock pulser). 0nitially Q
1
6 Q
2
6 7
!.( Design a cobinational circuit with three input )/ y/ and ./ and three outputs (/ , and 5.
when the binary input is 7/ 1/2 or +/ binary output is 2 greater than the input when the binary
input is '/ 2/ 3 or 4 the binary output is 2 less than the input.
Q.9 Define critical race condition with the help of tiing diagra.
Q.17 Design an #!: to check the sequence 17117.
TUTORIAL N" )
Q 3.2/ 3.3/3.4/ 3.9 3.17/ 3.11/ 3.12/ 3.1+/ 3.1' (part a and c)/ 3.12/ 3.13/ 3.14
;nsolved questions at the end of <a=ski ch 3
2
!
)
*
1
+
1
!
1
!
)
+
)
*
)
1
1
a
1
2
a
!
1
Cl"#$
!
)
*
1
+
1
!
1
!
)
+
)
*
)
1
1
a
1
2
a
!
1
Cl"#$
Cl"#$
B
B'
+
!
$
+
!
$
%
&
Cl"#$
B
B'
+
!
$
+
!
$
%
&
TUTORIAL NO. ,
Q. 1) !tating fro state 77 is in the state diagra in figure 1 1/ deterine the state
transitions and output sequence that will be generated when an input sequence of
717711771 is applied. ;n
#igure > 1
Q. 2) "educe the nuber of states in the following state table and tabulate the reduced state
table.
-S NS O.-
/ 0 0 / 0 1 /0 0 / 0 1
a f b 7 7
b d c 7 7
c f c 7 7
d g a 1 7
e d c 7 7
f f b 1 1
g g b 7 1
h g a 1 7
Q. +) #or the state table in question 1 2. find the output sequence generated with an input
sequence 71117717711. "epeat the question for reduced state table
+
00
10
11 01
0.0
1.0 0.1
1.0
0.1
0.1
1.0
1.0
00
10
11 01
0.0
1.0 0.1
1.0
0.1
0.1
1.0
1.0
D 1
Cl"#$
! D 1
Cl"#$
!

001
100
000
011
1.1
1.0
0.0
0.0
1.1
010
1.1
0.0
1.1
0.0
0.0
001
100
000
011
1.1
1.0
0.0
0.0
1.1
010
1.1
0.0
1.1
0.0
0.0
#igure 1 +
Q. ') (naly.e the circuit of figure 1 + and prove that it is equivalent to & #lip #lop.
Q. 2) ( sequential circuit has + flip flops. (/,/5 one input )- and one output y. &he state
diagra is given in figure 1 '. &he circuit is to be designed by treating the unusual
states as don*t care conditions. &he final circuit ust be analy.ed to ensure that it is
self>correcting.
(a) ;se D #lip #lop in the design
(b) ;se & #lip #lop in the design.
#igure 1 '
Q. 3) #or the state table given in figure. ?btain the state diagra/ if possible/ the reduced
state table @ design using $> %##.
-RESENTATION NE/T STATE OUT-UT
) 6 7 ) 6 1 A
7
2
7
1
7
7
7
2
7
1
7
9
7
2
7
1
7
7
)67 )61
7 7 7 1 7 1 7 7 1 7 7
7 7 1 7 1 1 7 1 7 7 7
7 1 7 1 7 1 1 7 7 7 7
7 1 1 1 1 7 7 7 7 1 7
1 7 7 7 1 1 7 1 7 7 7
1 7 1 1 7 1 7 7 1 1 1
1 1 7 1 1 7 1 1 1 7 1
1 1 1 1 1 7 7 7 7 1 7

3.1B/ 3.19/ 3.27/ 3.22
;nsolved questions at the end of <a=ski ch 3
TUTORIAL NO. 1
0pleent the following Datapaths
'
Q1 su6 i
x
Q2 su6 i i
x a
Q+ su 6 i i i
b x a +
Q'su6
i i i
c x x + +
2
Q2 Dra>w the state diagra for the following sequences
a) 71171
b) 77111
c) 7171
&here are soe errors in Q 3/ 4/ B 1 will be changed in class
Q3 &he state diagra of a control unit is shown in figure below. 0t has f' states and 2
inputs ) and y. Draw the equivalent (!: chart.
Q.4) Design a (!: chart with ' bit register (/ , and 5 to perfor the following
operations.
a) &ransfer 2 binary nubers to ( and , when a start signal is enabled.
71
11
17
77
C67
C67
C67
C61
A61
A67
C61
y61
C61/ A67
2
A67
C61/ A61
b) 0f ( D , shift left the contents of ( and transfer the result to register 5.
c) 0f ( E , shift right the contents of , and transfer the result to register 5.
d) 0f ( 6 , transfer the nuber to the register 5 unchanged.

Q.B) Draw the state diagra for the following (!: chart.
TUTORIAL NO. 5
Q. 1) Frite short note on the following data ob=ect.
(a) 5onstant (b) Gariable (c) !ignal (d) #ile
Q. 2) Define the following and give e)aples
(a) !calar type (b) 5oposite type (c) (ccess types (d) #ile
type
Q. +) Frite short notes on operations.
(a) Hogical (b) "elational (c) !hift (d) (dding
(c) :ultiplying (d) :iscellaneous.
Q. ') Frite short notes on
(a) 5(!I !tateent (d) J;HH !tateent (c) H??K !tateent
(d) IC0& !tateent (e) JIC& !tateent (f) (!!I"&0?J
!tateent
(g) "IK?"& !tateent (h) <IJI"05 !tateent (i) <IJI"(&I
!tateent (=) ,H?5% !tateent (k) Kackage dilation body (l)
(ttributes
Q. 2) Frite the differences between concurrent @ sequential signal assignent.
.
TUTORIAL NO. 2
3
Q. 1) I)plain how the od operator works
2 od +62
>2 od + 61
2 od(>+) 6>1
>2 od (>+)6 >2
Q2 Fhat is the difference between stdLlogic and stdLulogic. I)plain.
Q+ Fhat are attributesM
#or the following find different attributes for test/ (and set
&ype test is range 7 to 1I2-
&ype ( is range 21 to +7-
&ype set is(unkown/ high/ low/ undriven)-
Q' Fhat is assert stateent. #or a !" #lipgflop to work properly why we assert
!6*1* nand "6*1* M
5an we use the stateent !6*1* and "6*1*
Q2 Frite a while looN that calculates the e)ponential function of ) to an accuracy of one part
in 17
'
by suing the ters of the following series:
+ + + + + + =
O + O 2 1
1 ) e)p(
+ 2
x x x
x
Q3 !olve the following:
,P77711177Psll'
,P71771117Psll>2
,P717111117Psrl+
,P17711771Psrl>2
,P177171111Psra+
,P77771111 1Psrl+
,P71117717Pror4
,P71117717Prol2
TUTORIAL NO. 3
Q1 Fhat is the difference between three types of odelling in vhdl. <ive an e)aple
of i)ed ode odelling
Q2 <iven the following signal (
8D6 transport ( after 17 ns
+ 4 9 1+ 22 24 29 +7 '2
4
AD6 re=ect 2 ns inertial ( after 17 ns-
Draw 8 and A.
Frite the structural code for (Q+/'/ 2/3/4)
2:1 :;C
#ull subtractor
3.9/ 3.17 and 3.11 of <a=ski
0nclude a configuration for the ain progra
QB Frite signal drivers for following signal assignent stateents:
(a) Krocess
begin
Q..
8D6 + after 3 ns/ '2 after 2 ns/ 17 after 1' ns-
Ind process-
(b) process
begin
Q.
8D6 transport 17 after 2 ns-
8D6 transport '2 after + ns-
8D6 transport +7 after 12 ns-
Ind process-
Q.9 Frite signal drivers for following signal assignent stateents:
(a) process
begin
8D617 after 17ns-
8D6 12 after 12 ns-
8D6 re=ect 12 ns inertial 22 after 27 ns-
8D6 +7 after 12 ns-
Ind process-
(b) process
begin
8D6 1 after 2 ns/ 2 after 9 ns/ B after 17 ns/ 3 after 12 ns-
8D6 re=ect ' ns inertial 3 after 12ns/ 27 after 27 ns-
wait-
end process-
TUTORIAL NO. (
Q 1Dataflow code for D/ !" and & flip flops
Q2 2 Dataflow and behavioural code for od + counter
Q+ Dataflow for behavioural code for serial in serial out register
Q' dataflow and behavioural code for shift register
B
Q 2 Fhat is library and packageM I)plain the use of arith package with a n e)aple.
Q3 ,inary ultiplier
Q4 Frite ,ehavioral code for
Kriority encoder/ $% flip flop/ aster slave & flip flop/
QB Frite the GRDl code for <eneric (JD/ J(JD/ J?"/ C?"/ CJ?"/ ?" gates
Q9 $%## (all + odels) with presetSwithout preset @ clear.
Q.17 Frite the GRDH code for ,i>Directional shift register.
TUTORIAL NO. 4
Q. 1) Frite GRDH progra for a digital clock
Q2 Frite GRDl code for the following :oore #!:
Kr state CA677 CA671 CA617 CA611 ?utput 8
!7 !1 !2 !7 !1 7
!1 !7 !1 !7 !2 1
!2 !2 !7 !7 !7 1
Q+ Frite GRDl code for the following :ealy #!:
F56ue )
!1 7 57 2 89d 3 Frite GRDH codes for 3.12/ 3.1+ and 3.1' and 3.1B of <a=ski
TUTORIAL NO. 10
Q1 I)plain set up tie/ hold tie and clock skew
Q2 Fhat is guarded signal assignent. <ive an e)aple.
Q+ Frite GRDH code for a vending achine (Design your own achine)
Q' Frite GRDH code for a traffic light controller (Design your own controller)
Q2 Frite a note on D"(:. Row it is different fro "(:
9
T
1
T
0
T
)
T
,
0.1
1.0
0.0 1.1
0.0
0.1
1.1
0.0
T
1
T
0
T
)
T
,
0.1
1.0
0.0 1.1
0.0
0.1
1.1
0.0
Q3 Fhat are KHD/sM I)plain K"?:.
Q4Differentiate between K"?:/ K(H and KH(.
QB Fhat are functions and subprogras. <ive e)aple.
Q9 Fhat are RDH*sM Fhy they are used. Frite steps of (!05 design using 5(D tools.
Q17 . Fhat are signal drivers. Fhen does a ultiple driver stateent failM
17

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AMITY SCHOOL OF ENGINEERING & TECHNOLOGY

DIGITAL CIRCUITS & SYSTEM II (BTE 501)

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