This document describes an experiment to study the input and output characteristics of an NPN transistor in a common emitter configuration. The objectives are to determine the input and output characteristics and to observe the active, saturation, and cutoff regions of the transistor. The experiment involves connecting a circuit with an NPN transistor, resistors, and a multimeter. Procedures are outlined to vary the base current and collect emitter current and collector voltage values at different collector-emitter voltages. A PSpice simulation of the circuit is also required to generate the input and output characteristic curves.
This document describes an experiment to study the input and output characteristics of an NPN transistor in a common emitter configuration. The objectives are to determine the input and output characteristics and to observe the active, saturation, and cutoff regions of the transistor. The experiment involves connecting a circuit with an NPN transistor, resistors, and a multimeter. Procedures are outlined to vary the base current and collect emitter current and collector voltage values at different collector-emitter voltages. A PSpice simulation of the circuit is also required to generate the input and output characteristic curves.
This document describes an experiment to study the input and output characteristics of an NPN transistor in a common emitter configuration. The objectives are to determine the input and output characteristics and to observe the active, saturation, and cutoff regions of the transistor. The experiment involves connecting a circuit with an NPN transistor, resistors, and a multimeter. Procedures are outlined to vary the base current and collect emitter current and collector voltage values at different collector-emitter voltages. A PSpice simulation of the circuit is also required to generate the input and output characteristic curves.
This document describes an experiment to study the input and output characteristics of an NPN transistor in a common emitter configuration. The objectives are to determine the input and output characteristics and to observe the active, saturation, and cutoff regions of the transistor. The experiment involves connecting a circuit with an NPN transistor, resistors, and a multimeter. Procedures are outlined to vary the base current and collect emitter current and collector voltage values at different collector-emitter voltages. A PSpice simulation of the circuit is also required to generate the input and output characteristic curves.
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The University Of Asia Pacific
Department of Computer Science & Engineering
ECE 202 Experiment No: 05 Name of the Experiment : Stuy of !"P"! Common Emitter Transistor# Objective: To etermine the input an the output characteristics of an !"P"! transistor in Common Emitter $CE% configuration#
Theory: Transistor has t&o p"n 'unctions( one is ca))e the emitter 'unction an other is ca))e the co))ector 'unction# *hen transistor is use as an amp)ifier( it is operate in active moe# +n active moe( emitter 'unction is for&ar ,iase an co))ector 'unction is reverse ,iase# Figure: 1 Emitter current is given ,y( + E - + . / + C - 0$1/%23 + C *here( - + C 2 + . is ca))e common emitter gain# +n goo transistor + C 44+ . i#e( 441# + C can a)so ,e e5presse as + C - + .
&here( - 2$1/%# is ca))e common ,ase current gain# 6or goo transistor( is c)ose to unity# Proper c ,iasing of a transistor is a prere7uisite for proper operation as an amp)ifier# The purpose of the ,iasing is to fi5 the + C $c% an 8 CE $c%# .ut + C is a function of temperature( 8 .E an # +t is esira,)e to esign a ,iasing circuit &here + C is insensitive to change in # *hen E". 'unction is for&ar ,iase an C". 'unction is reverse ,iase( the transistor operates in active moe# 6or saturation moe of operation( ,oth 'unction are for&ar" ,iase# Cut"off region operation re7uires that ,oth E". an C". 'unctions ,e reverse ,iase# The inverte active operation occurs &hen E". is reverse ,iase an C". is for&ar ,iase#
Equipments: n"p"n transistor $c92:% one piece ;eesistor $2<( 1<( 500 ( 100 % =u)timeter .rea ,oar 1K 100K + VRB - + VBE - +VCE - + VRC - Circuit Diagrams: Figure: Common Emitter Configuration !roce"ure: 1# Connect the circuit as sho&n in fig#2# 2# 6irst set 8cc - 108# App)y vo)tage to ."E 'unction# A'ust the va)ue of 8 CC so that 8 CE is >ero# 8ary 8 .. an measure 8 .E for ifferent va)ues of + .# ?# ;epeat the a,ove e5periment for 8 CE - 1 8o)t# @# 8ary 8 .. so that + . is a,out 10 A# 8ary 8 CE in steps of 2#5 vo)ts an measure 8 CE an + C# 5# ;epeat the e5periment for + . - 20 A an ?0 A#
#imu$tion: Simu)ate the input an output characteristics curve of circuit sho&n in fig# 2 using Pspice Te5t Eitor# %#ubmit the report part at the &ab' Course No: ECE ( Expt) No: (* +egistration No: #emester: +o$$ No: Date: +eport: Data: 1 P)ot output an input characteristics of the n"p"n CE transistors in the graph paper an a% =arA active( saturation an cut"off regions of the characteristics# ,% Ca)cu)ate the ear)y vo)tage from the output characteristics# c% Discuss the effect of changing 8 CE on the input characteristics# % Discuss the effect of changing on the output characteristics# 2# *hat are the ro)e of the 2< an 1< fi5e resistors in the circuits B# ?# *rite the Pspice Te5t Eitor program use to simu)ate the input an output characteristics curve of circuit sho&n in fig# 2# @# Discussion:
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